CMP0417AA4-G70E Просмотр технического описания (PDF) - FIDELIX
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CMP0417AA4-G70E Datasheet PDF : 12 Pages
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CMP0417AAx-E
CMOS LPRAM
CAPACITANCE1) (f=1MHz , TA=25’C)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Output capacitance
CIO
1. Capacitance is sampled, not 100% tested.
VIO=0V
-
8
pF
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
ILI VIN=VSS to VCC
-1
-
1
uA
Output leakage current
ILO /CS=VIH, /ZZ=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC
-1
-
1
uA
ICC1
Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, /ZZ=VIH,
VIN≤0.2V or VIN≥VCC-0.2V
-
Average operating current
ICC2
Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, /ZZ=VIH,
VIN=VIL or VIH
-
-
3
mA
-
25
mA
Output low voltage
VOL IOL=0.5mA
0.2VCCQ V
Output high voltage
VOH IOH=-0.5mA
0.8VCCQ
V
Standby Current(TTL)
ISB /CS=VIH, /ZZ=VIH, Other inputs=VIH or VIL
-
-
0.3
mA
Standby Current(CMOS)
ISB1 /CS≥VCC-0.2V, /ZZ≥VCC-0.2V, Other inputs=0~VCC
-
Deep Power Down
Current1)
ISB0 /ZZ≤0.2V, Other inputs=0~VCC, No refresh(DPD)
-
ISB0a /ZZ≤0.2V, Other inputs=0~VCC, ¼ refresh area selection
-
-
70
uA
-
10
uA
-
40
uA
Low Power Modes
ISB0b /ZZ≤0.2V, Other inputs=0~VCC, ½ refresh area selection
-
-
50
uA
ISB0c /ZZ≤0.2V, Other inputs=0~VCC, All refresh area selection
-
-
70
uA
1. CMP0817BA2 & CMP0817BA5 products support DPD(Deep Power Down) Current
4
Revision 0.5
Aug. 2006
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