CMP0417AA0-F70I Просмотр технического описания (PDF) - FIDELIX

Номер в каталоге

Компоненты Описание

Список матч

CMP0417AA0-F70I

256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM

FIDELIX 

CMP0417AA0-I

WRITE CYCLE (4) (/UB, /LB controlled)

Address

/CS1

CS2

/UB, /LB

/WE

tAS(3)

Data in

Data Out

High-Z

tWC

tCW(2)

CMOS LPRAM

tWR(4)

tAW

tBW

tWP(1)

tDW

tDH

Data Valid

High-Z

1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with

asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write

ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to

the end of write.

2. tCW is measured from the /CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.

9

Revision 0.3

Sep. 2006

Share Link: