BS616LV1010AI(2001) Просмотр технического описания (PDF) - Brilliance Semiconductor
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BS616LV1010AI Datasheet PDF : 10 Pages
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BSI
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Vcc
CE
Vcc
t CDR
VIH
Data Retention Mode
VDR ≥ 1.5V
CE ≥ Vcc - 0.2V
BS616LV1010
Vcc
tR
VIH
AC TEST CONDITIONS
KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
WAVEFORM
INPUTS
MUST BE
STEADY
OUTPUTS
MUST BE
STEADY
AC TEST LOADS AND WAVEFORMS
3.3V
OUTPUT
1269 Ω
3.3V
OUTPUT
1269 Ω
INCLUDING
JIG AND
SCOPE
100PF
1404 Ω
INCLUDING
JIG AND
SCOPE
5PF
1404 Ω
FIGURE 1A
FIGURE 1B
OUTPUT
THEVENIN EQUIVALENT
667 Ω
1.73V
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
ALL INPUT PULSES
Vcc
GND
10%
→
90% 90%
←
→
10%
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 3.0V )
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
E1LQV
t
BA
t
GLQV
t
E1LQX
t
BE
t
GLQX
t
E1HQZ
t
BDO
t
GHQZ
t
AXOX
PARAMETER
NAME
t
RC
t
AA
t
ACS
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
(CE)
(LB,UB)
(CE)
(LB,UB)
(CE)
(LB,UB)
Output Disable to Output Address Change
BS616LV1010-70
MIN. TYP. MAX.
70
--
--
--
--
70
--
--
70
--
--
40
--
--
50
10
--
--
10
--
--
10
--
--
0
--
35
0
--
30
0
--
30
10
--
--
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS616LV1010
4
Revision 2.2
April 2001
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