MH4V36AM-7 Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC
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MH4V36AM-7 Datasheet PDF : 18 Pages
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Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
SWITCHING CHARACTERISTICS (Ta=0~70°C , Vcc=3.3V +/-0.3V, Vss=0V, unless otherwise noted , see notes 6,13,14)
Limits
Symbol
Parameter
-6
-7
Unit
Min
Max
Min
Max
tCAC
Access time from CAS
(Note 7,8)
15
20
ns
tRAC
Access time from RAS
(Note 7,9)
60
70
ns
tAA
Columu address access time
(Note 7,10)
30
35
ns
tCPA Access time from CAS precharge
(Note 7,11)
35
40
ns
tOEA Access time from OE
(Note 7)
15
20
ns
tCLZ
Output low impedance time from CAS low(Note 7)
5
5
ns
tOFF
Output disable time after CAS high
(Note 12)
0
15
0
15
ns
tOEZ
Output disable time after OE high
(Note 12)
0
15
0
15
ns
Note 6: An initial pause of 500 µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing RAS-Only refresh or CAS before RAS refresh).
Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods
(greater than 64 ms) of RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA)/VOL=0.4V(IOL=2mA) load 100pF.
The reference levels for measuring of output signal are 2.0V(VOH) and 0.8V(VOL).
8: Assumes that tRCD≥ tRCD(max) and tASC ≥ tASC(max).
9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max).
11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max).
12: tOFF(max) and tOEZ (max) defines the time at which the output achieves the high impedance state (IOUT ≤ I +/- 10 µAI) and is not reference to
VOH(min) or VOL(max).
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0 ~ 70 °C, Vcc=3.3V +/- 0.3V, Vss=0V, unless otherwise noted See notes 13,14)
Symbol
Parameter
tREF
Refresh cycle time
tRP
RAS high pulse width
tRCD Delay time, RAS low to CAS low
(Note15)
tCRP Delay time, CAS high to RAS low
tRPC
Delay time, RAS high to CAS low
tCPN
CAS high pulse width
tRAD
Column address delay time from RAS low
(Note16)
tASR Row address setup time before RAS low
tASC
Column address setup time before CAS low (Note17)
tRAH Row address hold time after RAS low
tCAH Column address hold time after CAS low
tDZC
Delay time, data to CAS low
(Note18)
tDZO
Delay time, data to OE low
(Note18)
tCDD Delay time, CAS high to data
(Note19)
tODD Delay time, OE high to data
(Note19)
tT
Transition time
(Note20)
Limits
-6
-7
Min
Max
Min
Max
64
64
40
50
20
45
20
50
10
10
0
0
10
10
15
30
15
35
0
0
0
10
0
10
10
10
15
15
0
0
0
0
15
15
15
15
1
50
1
50
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 13: The timing requirements are assumed tT =5ns.
14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) =tRAH(min) +2tH+tASC(min).
16: tRAD(max) is specified as a reference point only. If tRAD≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA.
17: tASC(max) is specified as a reference point only. If tRCD≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC.
18: Either tDZC or tDZO must be satisfied.
19: Either tCDD or tODD must be satisfied.
20: tT is measured between VIH(min) and VIL(max).
MIT-DS-0071-0.1
MITSUBISHI
ELECTRIC
( 4 / 18 )
Sep./19 /1996
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