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FM24C64VN

64K-Bit Standard 2-Wire Bus Interface Serial EEPROM

Fairchild Semiconductor 

Pin Descriptions

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the device.

Serial Data (SDA)

SDA is a bi-directional pin used to transfer data into and out of the

device. It is an open drain output and may be wire–ORed with any

number of open drain or open collector outputs.

Write Protect (WP)

If tied to VCC, PROGRAM operations onto the entire memory will

not be executed. READ operations are possible. If tied to VSS,

normal operation is enabled, READ/WRITE over the entire memory

is possible.

This feature allows the user to assign the entire memory as ROM

which can be protected against accidental programming. When

write is disabled, slave address and word address will be acknowl-

edged but data will not be acknowledged.

This pin has an internal pull-down circuit. However, on systems

where write protection is not required it is recommended that this

pin is tied to VSS.

Device Selection Inputs A2, A1 and A0 (as

appropriate)

These inputs collectively serve as “chip select” signal to an

EEPROM when multiple EEPROMs are present on the same IIC

bus. Hence these inputs should be connected to VCC or VSS in a

unique manner to allow proper selection of an EEPROM amongst

multiple EEPROMs. During a typical addressing sequence, every

EEPROM on the IIC bus compares the configuration of these

inputs to the respective 3 bit “Device/Page block selection”

information (part of slave address) to determine a valid selection.

For e.g. if the 3 bit “Device/Page block selection” is 1-0-1, then the

EEPROM whose “Device Selection inputs” (A2, A1 and A0) are

connected to VCC-VSS-VCC respectively, is selected.

Device Operation

The FM24C64 supports a bi-directional bus oriented protocol. The

protocol defines any device that sends data onto the bus as a

transmitter and the receiving device as the receiver. The device

controlling the transfer is the master and the device that is

controlled is the slave. The master will always initiate data

transfers and provide the clock for both transmit and receive

operations. Therefore, the FM24C64 will be considered a slave in

all applications.

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW.

SDA state changes during SCL HIGH are reserved for indicating

start and stop conditions. Refer Figure 1.

Start Condition

All commands are preceded by the start condition, which is a

HIGH to LOW transition of SDA when SCL is HIGH. The FM24C64

continuously monitors the SDA and SCL lines for the start condi-

tion and will not respond to any command until this condition has

been met. Refer Figure 2.

Stop Condition

All communications are terminated by a stop condition, which is a

LOW to HIGH transition of SDA when SCL is HIGH. The stop

condition is also used by the FM24C64 to place the device in the

standby power mode. Refer Figure 2.

FM24C64 Array Addressing

During Read/Write operations, addressing the EEPROM memory

array involves in providing 2 address bytes, “Word Address 1” and

“Word Address 0." However on FM24C64 only the 5 least signifi-

cant bits (LSB) of “Word Address 1” byte are used in decoding the

access location. The remaining 3 bits are not used and are

recommended to be set to “0." All 8 bits of the “Word Address 0”

byte are used in decoding the access location.

FM24C64 Rev. C

8

www.fairchildsemi.com

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