81C4256A-10 Просмотр технического описания (PDF) - Fujitsu
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81C4256A-10 Datasheet PDF : 29 Pages
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MB81C4256A-60
MB81C4256A-70
MB81C4256A-80
MB81C4256A-10
Not Recommended for New Design
RECOMMENDED OPERATING CONDITIONS
Parameter
Notes Symbol Min
Typ
Max
Supply Voltage
VCC
4.5
5.0
5.5
1
VSS
0
0
0
Input High Voltage, all inputs
1
VIH
2.4
—
6.5
Input Low Voltage, all inputs
1
VlL
-2.0
—
0.8
Input Low Voltage, DQ(*)
1
VILD
-1.0
—
0.8
Note: * : Undershoots of up to -2.0 volts with a pusle width not exceeding 20 ns are acceptable.
UnIt
V
V
V
V
Ambient
Operating Temp
0°C to +70°C
FUNCTIONAL OPERATION
ADDRESS INPUTS
Eighteen input bits are required to decode any four of 1,048,576 cell addresses in the memory matrix. Since only nine address bits
are available, the column and row inputs are separately strobed by CAS and RAS as shown in Figure 1. First, nine row address bits
are input on pins A0-through-A8 and latched with the row address strobe (RAS) then, nine column address bits are input and latched
with the column address strobe (CAS). Both row and column addresses must be stable on or before the falling edge of CAS and
RAS respectively.The address latches are of the flow-through type; thus, address information appearing after tRAH (min) + tT is auto-
matically treated as the column address.
WRlTE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated; when WE is High, a
read cycle is selected. During the read mode, input data is ignored.
DATA INPUT
Input data is written into memory in either of three basic ways—an early write cycle, an OE (delayed) write cycle, and a read-modfy-
write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch strobe. In an early write cycle, the input
data (DQ1-DQ4) is strobed by CAS and the setup and hold times are referenced to CAS because WE goes Low before CAS. In a
delayed write or a read-modify-write cycle, WE is set low after CAS; thus, input data is strobed by WE, and setup and hold times are
referenced to the write-enable signal.
DATA OUTPUT
The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical to that of the input;
the output buffers remain in the high-impedance state until the column address strobe goes Low. When a read or read-modify-write
cycle is executed, valid outputs are obtained under the following conditions:
tRAC : from the falling edge of RAS when tRCD (max) is satisfied.
tCAC : from the falling edge of CAS when tRCD is greater than tRCD, tRAD (max).
tAA : from column address input when tRAD is greater than tRAD (max).
tOEA : from the falling edge of OE when OE is brought Low after tRAC, tCAC, or tAA.
The data remains valid until either CAS or OE returns to a High logic level. When an early write is executed, the output buffers
remain in a high-impedance state during the entire cycle.
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