VV5850 Просмотр технического описания (PDF) - Vision
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VV5850 Datasheet PDF : 41 Pages
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VISION V V 6850 & 5850 Sensors: Product Datasheet Revision 1.0
Horizontal Shift Register
The Horizontal Shift Register is clocked by the Pixel Clock, PCK. Columns are read out, from left
to right, by the Line Start pulse, LS, propagating along the Horizontal Shift Register. The LS pulse
must be four PCK periods long, with the first valid pixel being sampled after the falling edge (see
DETAILED TIMING for exact relationship). To avoid bandwidth limitations within the output stage
causing cross talk problems between the colours in a colour pixelated sensor, the horizontal shift
register either reads out the odd or the even columns, under control of the EC signal.
In order to read valid pixel data, the Pixel Read input to the Read VSR, PXRD, must be high. (To
‘skip’ lines, for example as in Cine mode, PXRD must be held low during the two extra LCK peri-
ods.) When reading out either the even columns (EC=1) or the odd columns (EC=0) it is the
central 400 pixels of the 402 pixels read out that are valid. In Cine mode (Selected with bit CR[3]
y in the Control Register), every second pixel within a row is read out; of the 202 pixels read out for
r either EC=1 or EC=0, the central 200 pixels are valid.
Even line
LCK
aOdd Line
EVEN
PXRD
AVO
Even pixels Odd pixels
i
n
Even pixels
Odd pixels
LS
EC
CINE mode:
Even line
l i mOdd Line
Even line
LCK
EVEN
PXRD
r e Even Odd
AVO
LS
P
EC
Even Odd
Even Odd
Skip two lines
The HCLRB input (active low) clears the HSR to all zeros. HCLRB can also be used, for example,
to prematurely end a line scan, perhaps when only part of the image is required.
Note: The power-on reset signal, RSTB, should be used to drive HCLRB (and VCLRB for the
Vertical Shift Registers) at power up.
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