KE5B256B1CFP Просмотр технического описания (PDF) - KAWASAKI MICROELECTRONICS

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KE5B256B1CFP

ADDRESS PROCESSOR

KAWASAKI MICROELECTRONICS 

1. Features

Address Processor KE5B256B1

1.1 Introduction

KE5B256B1 is a 256k-bit CAM (Content Addressable

Memory) device with a new architecture. The main func-

tion of the LSI is fast searching of data on the search data

table stored in CAM. User can define the row/column table

size flexibility. The width of one entry in the search data

table can be selected from 32 bits to 256 bits, in increments

of 32 bits (1 segment). User can define the area to be

searched in an entry freely in terms of the position and bit

width. The search operation is executed for each segment,

and the cycle time is 80ns with the fast operation charac-

teristic of CAMs. KE5B256B1 provides 3 ports, an Input

Port, Output Port and CPU Port. These ports are designed

to have the most appropriate functionality.

The Input Port, which is only used for inputting the key

data, provides the programmable input data formatter and

programmable sequencer. These capabilities enable the

formatting of the incoming key data and flexible search

operation with any table column as a pre-determined se-

quence by writing into the Input Port.

Therefore, user can execute complex search operations

quickly. The search results can be output by flag pin and

by register reading from the Output Port or the CPU Port.

The Output Port is only used for outputting the search re-

sults. Like the Input Port, it has a programmable se-

quencer. The Output Port can output search results auto-

matically according to a pre-determined sequence by read-

ing from the Output Port.

the search table data of 32 bits. The upper 16 bits or the

lower 16 bits of the segment can be read/written with the

same address using the endian function.

Multiple devices can be easily cascade-connected in order

to increase the number of entries in the CAM table without

external logic. The extended CAM realized by cascade

connection can be treated as if it were one continuous table

in one device, because priority control is done internally

between devices.

However, the number of segments forming one entry in the

search data table must be the same in all devices (even if

the devices are not cascade connected).

This device must arbitrate between ports to protect against

data destruction caused by simultaneous access from plu-

ral ports. User can select two methods of arbitration. One

is an internal arbitration mode which restricts the device to

internal operation by port-dependent modes (CPU mode,

IP mode, OP mode, IOP mode). In this case, the device

determines whether the device receives operations from

every port or not. The other is external arbitration. In this

case, simultaneous access from every port is not permitted.

However, user can decrease the execution cycles, because

instead of external arbitration, mode restriction is not ap-

plied. User can select either method according to the re-

quired applications.

The CPU Port is used for the definition of the search table,

the table configuration/maintenance and the configuration

of the Input Port and the Output Port . The CPU Port has

registers and commands by which user can realize func-

tions easily. The registers can be accessed with direct ad-

dressing, and there are various effect commands for table

maintenance. The input/output data bus is 16 bits in width.

An endian function is supported to make it easy to access

1-1

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