DM9102 Просмотр технического описания (PDF) - Davicom Semiconductor, Inc.
Номер в каталоге
Компоненты Описание
Список матч
DM9102 Datasheet PDF : 63 Pages
| |||
T Features
T Single chip LAN controller integrated Fast Ethernet MAC,
PHY and transceiver
T Compliant with IEEE 802.3u 100BASE-TX, IEEE 802.3
10BASE-T and ANSI X3T12 TP-PMD standard
T Direct interface to the PCI bus & fully compliant with PCI
specification 2.1
T PCI bus master architecture
T Support PCI bus burst mode data transfer with
programmable burst size
T EEPROM 93C46 interface to store configuration
information and user defined message
T Support up to 256K bytes Boot ROM interface
T Two large independent receive FIFO (4K) & transmit
FIFO (2K) with programmable FIFO threshold and full
packet burst processing
DM9102
10/100Mbps Single Chip LAN Controller
T Support automatic packet deletion for runt packets and
packet re-transmission with no FIFO reload
T Support Full/Half Duplex operation
T Physical, broadcast address recognition and 512-bit hash
table algorithm for multicast address filtering
T Compliant with IEEE802.3u Auto-negotiation protocol for
automatic link type selection
T High performance 100Mbps clock generator and data
recovery circuit
T Digital clock recovery circuit using advanced digital
algorithm to reduce jitter
T Adaptive equalization circuit and Baseline wandering
restoration circuit for 100Mbps receiver
T Provides Loopback mode for easy system diagnostics
T 128 pin QFP with CMOS process
4
Final
Version: DM9102-DS-F03
August 30, 2000
Share Link: 