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FS6012-02 Просмотр технического описания (PDF) - AMI Semiconductor

Номер в каталоге
Компоненты Описание
Список матч
FS6012-02
AMI
AMI Semiconductor AMI
FS6012-02 Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
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August 1998
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
TYPE
NAME
DESCRIPTION
1
DI
SCL
Serial Data Clock
2
DIO
SDA
Serial Data Input/Output
3
DID
ADDR
Address Select Bit
4
P
VSS
Ground
5
AI
XIN
VCXO Feedback
6
AO
XOUT
VCXO Drive
7
AI
XTUNE
VCXO Tune
8
P
VDD
Power Supply (+5V)
9
DID
PSEL1
PCLK Select MSB
10
DID
PSEL0
PCLK Select LSB
11
P
VSS
Ground
12
DO
PCLK
Processor Clock Output
13
DO
UCLK
Utility Clock Output
14
P
VDD
Power Supply (+5V)
15
DO
ACLK
Audio Clock Output
16
DO
CLK27
Reference Clock Output
3.0 Functional Block Description
3.1 Phase-Locked Loops
Each one of the three on-chip PLLs in the FS6012 is a
standard frequency- and phase-locked loop architecture.
Each PLL multiplies the reference oscillator to the desired
frequency by a ratio of integers. The frequency multipli-
cation is exact.
An onboard ROM contains the PLL settings that control
the relationship between reference and output frequen-
cies. The I2C-bus communications are used to choose a
desired ROM setting. Custom frequency selections are
available for this device. Contact your local AMI Sales
Representative for more information
3.2 Output Tristate Control
All four clock outputs of the FS6012 may be tristated to
facilitate circuit board testing. To place the outputs in
tristate mode, follow this sequence:
1. force XIN low (i.e. ground)
2. apply power to the device
3. wait until the internal power-on reset has de-asserted
4. apply a negative-going transition to the PSEL0 pin
Outputs may be re-enabled by removing and reapplying
VDD to the device. To re-enable outputs without remov-
ing power, apply a positive-going transition to the XIN in
and follow it with a negative-going transition on the
PSEL0 pin.
,62
2
8.19.98

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