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11257-801

Low-Skew Clock Fanout Buffer ICs

AMI Semiconductor 

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April 1999

Figure 6: Random Register Write Procedure (I2C-bus)

S DEVICE ADDRESS W A REGISTER ADDRESS A

DATA

AP

7-bit Receive

Device Address

Register Address

Acknowledge

Data

Acknowledge

START

Command

WRITE Command

From bus host

to device

From device

to bus host

STOP Condition

Acknowledge

Figure 7: Random Register Read Procedure (I2C-bus)

S DEVICE ADDRESS W A REGISTER ADDRESS A S DEVICE ADDRESS R A

DATA

AP

7-bit Receive

Device Address

Register Address

Acknowledge

START

Command

WRITE Command

From bus host

to device

7-bit Receive

Device Address

Repeat START

Acknowledge

From device

to bus host

Data

Acknowledge

READ Command

Figure 8: Sequential Register Write Procedure (I2C-bus)

STOP Condition

NO Acknowledge

S DEVICE ADDRESS W A REGISTER ADDRESS A

DATA

A

DATA

A

DATA

AP

7-bit Receive

Device Address

Register Address

Acknowledge

Data

Acknowledge

START

Command

WRITE Command

From bus host

to device

From device

to bus host

Data

Acknowledge

Figure 9: Sequential Register Read Procedure (I2C-bus)

Acknowledge

S DEVICE ADDRESS W A REGISTER ADDRESS A S DEVICE ADDRESS R A

DATA

A

Data

Acknowledge

STOP Command

DATA

AP

7-bit Receive

Device Address

Register Address

Acknowledge

START

Command

WRITE Command

From bus host

to device

7-bit Receive

Device Address

Repeat START

Acknowledge

From device

to bus host

Data

Acknowledge

READ Command

,62

7

Acknowledge

Data

NO Acknowledge

STOP Command

4.5.99

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