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QS5LV919

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

Integrated Device Technology 

QS5LV919

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

INDUSTRIAL TEMPERATURE RANGE

The frequency relationship shown here is applicable to all Q outputs (Q0, Q1,

Q2, Q3 and Q4).

25 MHz feedback signal

50 MHz signal

2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP

In this application, the 2Q output is connected to the FEEDBACK input. The

internal PLL will line up the positive edges of 2Q and SYNC, thus the 2Q

frequency will equal the SYNC frequency. The Q/2 output will always run at

1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency.

Note that with 2Q as feedback, the maximum input frequency is 100MHz for FS

= HIGH

LOW

25 MHz

input

HIGH

OE/RST Q5

Q4

FEEDBACK

REF_SEL

SYNC(0)

VCC(AN)

QS5LV919

PE

2Q

Q/2

12.5 MHz

signal

Q3

25 MHz

"Q"

Clock

Q2

Outputs

50 MHz feedback signal

HIGH

GND(AN)

FQ_SEL

Q0

Q1 PLL_EN

LOW

50 MHz

input

OE/RST Q5

Q4

FEEDBACK

REF_SEL

SYNC(0)

VCC(AN)

PE

QS5LV919

GND(AN)

2Q

Q/2

12.5 MHz

input

Q3

25 MHz

"Q"

Clock

O u tp u ts

Q2

HIGH

HIGH

Allowable Input Frequency Range:

20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH)

10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)

Figure 2b. Wiring Diagram and Frequency Relationships with

Q4 Output Feedback

FQ_SEL

Q0

HIGH

Q1 PLL_EN

HIGH

Allowable Input Frequency Range:

40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH)

20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)

Figure 2a. Wiring Diagram and Frequency Relationships with 2Q

Output Feedback

1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP

In this application, the Q4 output is connected to the FEEDBACK input. The

internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4

frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The

Q/2 output will always run at 1/2 the Q frequency, and the 2Q output will run

at 2X the Q frequency.

1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP

In this application, the Q/2 output is connected to the FEEDBACK input. The

internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2

frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will

always run at 2X the Q/2 frequency, and the 2Q output will run at 4X the Q/2

frequency.

50 MHz signal

12.5 MHz feedback signal

HIGH

LOW

12.5 MHz

input

OE/RST Q5

FEEDBACK

Q4

2Q

Q/2

REF_SEL

SYNC(0)

Q3

VCC(AN)

QS5LV919

PE

Q2

GND(AN)

FQ_SEL

Q0

Q1 PLL_EN

25 MHz

"Q"

Clock

Outputs

HIGH

HIGH

Allowable Input Frequency Range:

10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH)

5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)

Figure 2c. Wiring Diagram and Frequency Relationships with

Q2 Output Feedback

8

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