W5100 Просмотр технического описания (PDF) - Unspecified

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W5100

single-chip Internet-enabled 10/100 Ethernet controller

Unspecified 

Document History Information

Version

Date

Descriptions

Ver. 1.0.0 Dec. 21, 2006 Released with W5100 Launching

Ver. 1.0.1

Jan. 10, 2006

LB bit in Mode register is not used .

W5100 is used only in Big-endian ordering.

Ver. 1.1.1

Jun. 19, 2007

Modified the OPMODE2-0 signals descriptions (P. 10)

Modified the TEST_MODE3-0 signals description (P.11)

Modified the Clock signals description (P.12)

Modified the LINKLED signal description (P.12)

Modified the explanation of RECV_INT in Sn_IR register (P. 27)

Replaced the reset value of Sn_DHAR register (0x00 to 0xFF, P. 30)

Modifted the explanation of Sn_DIPR, Sn_DPORT register(P. 31)

Replaced the reset value of Sn_MSS register (0xFFFF to 0x0000, P. 31)

Ver. 1.1.2 Sep. 28, 2007 Modified the Operating temperature (P. 63)

Ver. 1.1.3

Oct. 18, 2007

Changed the typing error “MISO signal” (P. 10)

Modified the SPI Timing diagram and description (P. 66)

Ver. 1.1.4 Oct. 18, 2007 Modified the diagram (P. 40)

Ver. 1.1.5 Nov. 11, 2007 Modified the Crystal Characteristics value (P. 67)

Ver. 1.1.6

Ver. 1.1.7

Jan. 30, 2008

Feb. 12, 2009

Modified the SEN signals description (P.10)

Changed the typing error “SCLK” (P. 66)

Changed the typing error “memory test mode” (P. 19)

Changed the description & type of clock signals (P. 12)

Ver. 1.1.8 Mar. 4, 2009

Remove “support SPI Mode 3” (P.5, P.61)

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