W5100 Просмотр технического описания (PDF) - Unspecified

Номер в каталоге

Компоненты Описание

Список матч

W5100

single-chip Internet-enabled 10/100 Ethernet controller

Unspecified 

SEN

SCLK

/SCS

MOSI

MISO

I

31

I

30

I

29

I

28

O

27

Strobe from MCU to read an internal

register/memory selected by ADDR[14:0]. This signal

is active low.

SPI ENABLE

This pin selects Enable/disable of the SPI Mode.

Low = SPI Mode Disable

High = SPI Mode Enable

If you don’t use SPI mode, then you tied this signal

to ‘0’.

SPI CLOCK

This pin is used to SPI Clock signal Pin.

SPI SLAVE SELECT

This pin is used to SPI Slave Select signal Pin. This

pin is active low

SPI MASTER OUT SLAVE IN

This pin is used to SPI MOSI signal pin.

SPI MASTER IN SLAVE OUT

This pin is used to SPI MISO signal pin.

1.2 PHY Signals

Symbol

RXIP

Type

I

RXIN

I

Pin No

5

6

Description

RXIP/RXIN Signal Pair

The differential data from the media is received on

the RXIP/RXIN signal pair.

TXOP

TXON

RSET_BG

OPMODE2-0

O

8

TXOP/TXON Signal Pair

O

9

The differential data is transmitted to the media on

the TXOP/TXIN signal pair.

O

1

PHY Off-chip resistor

Connect a resistor of 12.3 ㏀±1% to the ground.

Refer to the “Reference schematic”.

I

65, 64, OPERATION CONTROL MODE

63

[2:0] Description

000 Auto-negotiation enable with all capabilities

© Copyright 2008-2009 WIZnet Co., Inc. All rights reserved.

10

Share Link: