3. Block Diagram
16 Bits
Memory Controller
SPI Type
Flash
Control
DRAM
Control
LBC
Host
EJTAG
CPU RLX5281
I-Cache=16kB
D-Cache=8kB
I-Ram=40kB
D-Ram=8kB
LBC Host
LBC Host
NIC
Controller
Switch Controller CPU Port
L2 Address Lookup Engine
Packet Buffer
(SRAM 512Kbits)
MDC/
MDIO
LED
5 * Giga-bit
Ethernet PHY
RG/MII*1
RTL8198
Datasheet
25MHz Crystal
or 40MHz Clock
GPIO
UART *2
Clock Gen. &
Reset CKT
Timer
Interrupt
Controller
Lexra Bus
LBC Host
PCIE
Bridge
Controller
PHY
LBC Host
USB 2.0
Host +
1*PHY
LBC Host
NFBI
Figure 1. Block Diagram
IEEE 802.11n Gigabit Ethernet AP/Router Network Processor
5
Track ID: JATR-2265-11 Rev. 0.91