HIP050IP Просмотр технического описания (PDF) - Intersil
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HIP050IP Datasheet PDF : 7 Pages
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Block Diagram
HIP0050
EN
STR
SI
SCK
SO
(ENABLE)
(STROBE)
Q0
SERIAL
Q1
(SPI)
INPUT
Q2
REGISTER
(DATA IS
Q3
PARALLEL
Q4
OUTPUT
LATCHED
Q5
WHEN
STROBED)
Q6
Q7
OUTPUT DRIVER
(CHANNEL 1 OF 8)
OUTPUT
LATCH
POR
OC
SHUT-
DOWN
OVER-TEMPERATURE
SHUTDOWN W/HYS
S FAULT
R LATCH
DR#0
FLT
Output Control Logic Table
STROBE
8-BIT SERIAL DATA (LATCHED)
D1 D2 D3 D4 D5 D6 D7
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
OUTPUT
D8 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DR8
0 OFF OFF OFF OFF OFF OFF OFF OFF
0 ON OFF OFF OFF OFF OFF OFF OFF
0 ON ON OFF OFF OFF OFF OFF OFF
0 ON ON ON OFF OFF OFF OFF OFF
0 ON ON ON ON OFF OFF OFF OFF
1 OFF OFF OFF OFF ON ON ON ON
1 ON ON ON ON ON ON ON ON
2
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