CS5343-CZZ Просмотр технического описания (PDF) - Cirrus Logic
Номер в каталоге
Компоненты Описание
Список матч
CS5343-CZZ Datasheet PDF : 21 Pages
| |||
CS5343/4
4.6 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the MCLK, SCLK, and LRCK must be the same for all of the CS5343 and
CS5344 devices in the system.
5. FILTER PLOTS
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency (norm alized to Fs)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (norm alized to Fs)
Figure 8. Single-Speed Mode Stopband Rejection
Figure 9. Single-Speed Mode Transition Band
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
0 .4 6
0 .4 7
0 .4 8
0 .4 9
0 .50
0.51
0.52
Frequency (norm alized to Fs)
Figure 10. Single-Speed Mode Transition Band (Detail)
0 .10
0 .0 8
0 .0 6
0 .0 4
0 .0 2
0 .0 0
- 0 .0 2
- 0 .0 4
- 0 .0 6
- 0 .0 8
- 0 .10
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (norm alized to Fs)
Figure 11. Single-Speed Mode Passband Ripple
DS687A4
17
Share Link: 