AD9880 Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
Список матч
AD9880 Datasheet PDF : 64 Pages
| |||
AD9880
Table 5. Pin Function Descriptions
Pin
Description
INPUTS
RAIN0
Analog Input for the Red Channel 0.
GAIN0
Analog Input for the Green Channel 0.
BBAIN0
Analog Input for the Blue Channel 0.
RAIN1
Analog Input for the Red Channel 1.
GAIN1
Analog Input for the Green Channel 1.
BBAIN1
Analog Input for Blue Channel 1.
High impedance inputs that accept the red, green, and blue channel graphics signals, respectively. The three channels
are identical, and can be used for any colors, but colors are assigned for convenient reference. They accommodate
input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp
operation. (see Figure 3 for an input reference circuit).
Rx0+
Digital Input Channel 0 True.
Rx0−
Digital Input Channel 0 Complement.
Rx1+
Digital Input Channel 1 True.
Rx1−
Digital Input Channel 1 Complement.
Rx2+
Digital Input Channel 2 True.
Rx2−
Digital input Channel 2 Complement.
These six pins receive three pairs TMDS (Transition Minimized Differential Signaling) pixel data (at 10X the pixel rate)
from a digital graphics transmitter.
RxC+
Digital Data Clock True.
RxC−
Digital Data Clock Complement.
This clock pair receives a TMDS clock at 1× pixel data rate.
HSYNC0
Horizontal Sync Input Channel 0.
HSYNC1
Horizontal Sync Input Channel 1.
These inputs receive a logic signal that establishes the horizontal timing reference and provides the frequency
reference for pixel clock generation. The logic sense of this pin is controlled by serial register 0x12 Bits 5:4 (Hsync
polarity). Only the leading edge of Hsync is active; the trailing edge is ignored. When Hsync Polarity = 0, the falling
edge of Hsync is used. When Hsync Polarity = 1, the rising edge is active. The input includes a Schmitt trigger for noise
immunity.
VSYNC0
Vertical Sync Input Channel 0.
VSYNC1
Vertical Sync Input Channel 1.
These are the inputs for vertical sync.
SOGIN0
Sync-On-Green Input Channel 0.
SOGIN1
Sync-On-Green Input Channel 1.
These inputs are provided to assist with processing signals with embedded sync, typically on the green channel. The
pin is connected to a high speed comparator with an internally generated threshold. The threshold level can be
programmed in 10 mV steps to any voltage between 10 mV and 330 mV above the negative peak of the input signal.
The default voltage threshold is 150 mV. When connected to an ac-coupled graphics signal with embedded sync, it
produces a noninverting digital output on SOGOUT. (This is usually a composite sync signal, containing both vertical
and horizontal sync (Hsync) information that must be separated before passing the horizontal sync signal to Hsync.)
When not used, this input should be left unconnected. For more details on this function and how it should be
configured, refer to the Hsync and Vsync Inputs section.
EXTCLK/COAST
Coast Input to Clock Generator (Optional).
This input may be used to cause the pixel clock generator to stop synchronizing with Hsync and continue producing a
clock at its current frequency and phase. This is useful when processing signals from sources that fail to produce
horizontal sync pulses during the vertical interval. The Coast signal is generally not required for PC-generated signals.
The logic sense of this pin is controlled by Coast polarity (Register 0x18, Bits 6:5). When not used, this pin may be
grounded and input Coast polarity programmed to 1 (Register 0x18, Pin 5), or tied high (to VD through a 10 KΩ resistor)
and input Coast polarity programmed to 0. Input Coast polarity defaults to 1 at power-up. This pin is shared with the
EXTCLK function, which does not affect Coast functionality. For more details on Coast, see the description in the Clock
Generation section.
EXTCLK/COAST External Clock.
This allows the insertion of an external clock source rather than the internally generated PLL locked clock. This pin is
shared with the Coast function, which will not affect EXTCLK functionality.
Rev. 0 | Page 9 of 64
Share Link: 