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STLC3055Q

WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT

STMicroelectronics 

STLC3055

Figure 4. Metering pulse generation circuit.

CTTX1

Low Pass Filter

C1

BURST

SHAPING CS

GENERATOR

RLV

SQTTX

RLV

D0

CKTTX

CTTX2

Square wave pulse metering

shaping by the capacitor CS.

The waveform so generated is then filtered and

injected on the line.

The low pass filter can be obtained using the inte-

grated buffer OP1 connected between pin FTTX

(OP1 non inverting input) and RTTX (OP1 output)

(see fig.4) and implementing a "Sallen and Key"

configuration.

Depending on the external components count it is

possible to build an optimised application de-

pending on the distortion level required. In par-

ticular harmonic distortion levels equal to 13%,

6% and 3% can be obtained respectively with

first, second and third order filters (see fig.4).

The circuit showed in the "Application diagram" is

related to the simple first order filter.

Once the shaped and filtered signal is obtained at

RTTX buffer output it is injected on the TIP/RING

pins with a +6dB gain.

It should be noted that this is the nominal condi-

tion obtained in presence of ideal TTX echo can-

cellation (obtained via proper setting of RTTX and

CTTX). In addition the effective level obtained on

the line will depend on the line impedance, the

protection resistor value and the series switch

(SW1 or SW2) on resistance.

In the typical application (TTX line impedance

=200Ω , RP = 41Ω, SW1,2 on resistance = 9Ω

and ideal TTX echo cancellation) the metering

pulse level on the line will be 1.33 times the level

applied to the RTTX pin.

-

R1 R2 FTTX OP1

+

RTTX

CFL

C2

Sinusoidal wave

pulse metering

Required external components vs. filter order.

Order CFL R1 C! R2 C2 THD

1X

13%

2

X X X X 6%

3 X X X X X 3%

As already mentioned the metering pulse echo

cancellation is obtained by means of two external

components (RTTX and CTTX) that should match

the line impedance at the TTX frequency. This

simple network has a double effect:

Synthesise a low output impedance at the

TIP/RING pins at the TTX frequency.

Cut the eventual TTX echo that will be trans-

ferred from the line to the TX output.

Ringing

When this mode is selected STLC3055 self gen-

erate an higher negative battery (-70V typ.) in or-

der to allow a balanced ringing signal of typically

65Vpeak.

In this condition both the DC and AC feedback

loop are disabled and the SLIC line drivers oper-

ate as voltage buffers.

The ring waveform is obtained toggling the D2

control bit at the desired ring frequency. This bit in

fact controls the line polarity (0=direct; 1=re-

verse). As in the ACTIVE mode the line voltage

transition is performed with a ramp transition, ob-

taining in this way a trapezoidal balanced ring

waveform (see fig.5).

The shaping is defined by the CREV external

capacitor.

Selecting the proper capacitor value it is possible

to get different crest factor values.

The following table shows the crest factor values

7/22

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