CS22220 Просмотр технического описания (PDF) - Cirrus Logic

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CS22220

Wireless PCMCIA Controller

Cirrus Logic 

2 Features

Embedded ARM Core and System Support Logic

• High performance ARM7TDMI RISC processor core up to 77MHz

• 4KB integrated, one-way set associative, unified, write through cache

• Individual interrupt for each functional block

• Two 23-bit programmable (periodic or one-shot) general purpose timers

• 8 Dword (32-bits) memory write and read buffers for high system performance

• Abort cycle detection and reporting for debugging

• ARM performance monitoring function for system fine-tuning

• Programmable performance improvement logic based on system configuration

Enhanced Memory Controller Unit

• Programmable memory controller unit supporting SDRAM /async SRAM/Boot ROM/Flash

interface

• 16-bit data bus with 12-bit address supporting up to 4MB up to 103 MHz (100/133MHz SDRAM)

• 8-bit data bus with addressing support up to 1MB of boot ROM/Flash.

• Programmable SDRAM timing and size parameters such as CAS latencies and number of

banks, columns, and rows

• Flexible independent DMA engines for PCMCIA and digital radio functional units

FEC codec

• High performance Reed-Solomon coding for error correction (255:239 block coding)

• Reduces error probability of a typical 10e-3 error rate environment to 10e-9

• Programmable rate FEC engine to optimize channel efficiency

• Low latency, fully pipelined hardware encoding and decoding. Supports byte-wise single cycle

throughput up to 77MHz, with a sustain rate of 77MBps.

• Double buffering (63 Dword read/write buffer) to enhance system performance

Digital Radio MAC Interface

• Glue-less interface to 802.11b baseband transceivers

• Up to 11Mbps data rates

• 32 Dword transmit/receive FIFO

• Supports clear channel assessment (CCA)

Power Management

• Host (PCMCIA) ACPI compliant

• Programmable sleep timer for ARM core and system low power management

• Independent power management control for individual functional units

• Supports variable rate radio transmit, receive, and standby radio power modes

Clock and PLL Interface

• Single 44MHz crystal oscillator reference clock

• Internal PLL to generate internal and on board clocks

PCMCIA Interface

• 16 bit PCMCIA I/O target device supporting memory map or program I/O using 11 address bits

• Independent DMA controller to transfer data between PCMCIA and main memory

• Fully compliant with PCMCIA 2.1/JEIDA 4.2 standard

• Supports big endian and little endian (default) data formats

• Supports custom mode for embedded applications where the interface becomes a generic

memory address/data interface

Chip Processing and Packaging

• 208 FPBGA package and 0.18um state of the art CMOS process

• 1.8 V core for low power consumption. 3.3V I/O - 5V tolerant I/O

CS22220 Wireless PCMCIA Controller

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www.cirrus.com

DS557PP2 Rev. 3.0

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