CXB1455R Просмотр технического описания (PDF) - Sony Semiconductor

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CXB1455R

VGA/SVGA/XGA 24-bit Transmitter

Sony Semiconductor 

CXB1455R

Timing Chart

SFTCLK

Tir

Setup/hold times are referred from

falling edge in CKPOL = GND

rising edge in CKPOL = Vcc

REDxx

GRNxx

BLUxx

H/Vsync

CNTLx

2.0V

0.8V

Tif

Tsetup

Min. 2 (SFTCLK cycle)

1/Fsftclk

Dsftclk/Fsftclk

Tir

2.0V

0.8V

Tif

VSYNC

HSYNC

Min. 2

Min. 2

Min. 2

Min. 2

Min. 2

DE

VIH_T

Vth

VIL_T

Thold

VIH_T

VIL_T

RGB

CNTL There must be 2 SFTCLK cycles or more left between the CNTL edge and the HSYNC, VSYNC and DE edges.

Fig. 3. TTL input timing

SDATAP

SDATAN

Tor

80%

20%

Tof

Fig. 4. Serial output timing

100%

0%

–6–

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