Variable Split Band Inverter
3
MX214/224
1. Block Diagram
POWERSAVE
LOAD / LATCH
SERIAL CLOCK
ENABLE / MUTE
CLEAR / SCRAMBLE
Rx / Tx (SER / PAR)
A0
A1
A2
A3
A4
INPUT LATCHES
EN / MUTE
CLEAR / SCRAMBLE
Rx / Tx
ROM
(SERIAL DATA IN)
Rx IN
Tx IN
EN ⋅ PS ⋅ Rx
PS
BIAS
Rx
MUTE
BIAS
Tx ⋅ PS
Tx ⋅ PS
CK3
FILTER 3
PS
BIAS
FILTER 1
CKA
CKB
CTCSS
FC2
C5
Rx
FC1
Tx
C6
1MHz
OSC
XTAL / CLOCK
XTAL
1MHz
CLOCK
DIVIDER
CKA FC1 FC2 PS
CK3
CK4
CLOCK
DIVIDER
CKB CKB
CLOCK
SWITCHING
Rx / Tx
VDD
VBIAS
VSS
Rx
Tx
PS ⋅ EN ⋅ Tx
Rx
Rx
Tx
FILTER 4 SCRAMBLE
CK4
Σ
FILTER 2
CKA
Tx
CK4
Rx
CLEAR
BIAS
Tx OUT
PS + EN ⋅ Tx
BIAS
PS ⋅ MUTE ⋅ Rx
Rx OUT
BIAS
BIAS
PS + EN ⋅ Rx
Figure 1: Block Diagram
1998 MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480112.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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