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UT1553B/BCRT-ACA0 Просмотр технического описания (PDF) - Aeroflex UTMC

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UT1553B/BCRT-ACA0 Datasheet PDF : 61 Pages
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RAM
DATA
BCRT
ADDRESS
MEMORY
CONTROL
BUFFER
DUAL
TRANSCEIVER
ARBITRATION
XFMR XFMR
CPU
BUS A
BUS B
1553 BUS
Figure 3d. CPU/BCRT Interface -- DMA Configuration
.
BCRT
TIMERON
CHANNEL A CHANNEL B CHA/B
CHANNEL A
CHANNEL B
TXINHA
DUAL
TRANSCEIVER
TXINHB
Figure 4. Dual-Channel Transceiver
The BCRT also provides a TIMERON signal output and an
active channel output indicator (CHA/B) to assist in meeting
the MIL-STD-1553B fail-safe timer requirements (see
figure 4).
6.0 REMOTE TERMINAL
ARCHITECTURE
The Remote Terminal architecture is a descriptor-
based configuration of relevant parameters. It is composed
of an RT Descriptor Space (see figure 5) and internal, host-
programmable registers. The Descriptor Space contains
only descriptors. Descriptors contain programmable
subaddress parameters relating to handling message
transfers. Each descriptor consists of four words: (1) a
Control Word, (2) a Message Status List Pointer, (3) a Data
List Pointer, and (4) an unused fourth word (see figure 6.)
These words indicate how to perform the data transfers
associated with the designated subaddress.
A receive descriptor and a transmit descriptor are associated
with each subaddress. The descriptors reside in memory
and are listed sequentially by subaddress. By using the
index within the descriptor, the BCRT can buffer incoming
and outgoing messages, which reduces host CPU overhead.
This message buffering also reduces the risk of incoming
messages being overwritten by subsequent
incoming messages.
Each descriptor contains a programmable interrupt structure
for subsystem notification of user-selected message
transfers and indicates when the message buffers are full.
Illegalizing subaddresses, in normal and broadcast modes,
is accomplished by using programmable bits within the
descriptor (see the RT Functional Operation section on
next page).
BCRT-21

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