UT1553B/BCRT-ACA0 Просмотр технического описания (PDF) - Aeroflex UTMC

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UT1553B/BCRT-ACA0

UT1553B BCRT bus controller/remote terminal/monitor. Lead finish optional. Total dose none.

Aeroflex UTMC 

RAM

16 DATA

16 ADDRESS

BUFFERS

HOST

CPU

CONTROL

BCRT

(DUAL REDUNDANT)

DUAL

TRANSCEIVER

CONTROL/ARBITRATION

TRANSMITTER

TIMEOUT

XFMR XFMR

BUS A

BUS B

1553 BUS

Figure 3b. CPU/BCRT Interface -- Pseudo-Dual-Port RAM Configuration

5.4 RAM Interface

The BCRT’s RRD, RWR, and MEMCSO signals serve as

read and write controls during BCRT memory accesses. The

host subsystem signals RD, WR, and MEMCSI propagate

through the BCRT to become RRD, RWR, and MEMCSO

outputs to support a pseudo-dual-port. During BCRT-RAM

data transfers, the host subsystem’s memory signals are

ignored until the BCRT access is complete.

5.5 Transmitter/Receiver Interface

The BCRT’s Manchester II encoder/decoder interfaces

directly with the 1553 bus transceiver, using the TAO-TAZ

and RAZ-RAO signals for Channel A, and TBO-TBZ and

RBZ-RBO signals for Channel B.

CPU

BCRT-20

ADDRESS BUS

DATA BUS

SHARED

MEMORY

AREA

OE •

WE •

CS •

DMAR DMAG DMACK

BCRT

RRD RWR MEMCSO

Figure 3c. DMA Signals

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