UT1553B/BCRT-ACA0 Просмотр технического описания (PDF) - Aeroflex UTMC

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UT1553B/BCRT-ACA0

UT1553B BCRT bus controller/remote terminal/monitor. Lead finish optional. Total dose none.

Aeroflex UTMC 

Built-in memory management functions designed

specifically for MIL-STD-1553B applications aid processor

off-loading. The host needs only to establish the parameters

within memory so the BCRT can access this information as

required. For example, in the RT mode, the BCRT can store

data associated with individual subaddresses anywhere

within its 64K address space. The BCRT then can

automatically buffer up to 128 incoming messages of the

same subaddress, thus preventing the previous messages

from being overwritten by subsequent messages. This

buffering also extends the intervals required by the host

processor to service the data. Selecting an appropriate

MCLK frequency to meet system memory access time

requirements controls the memory access rate. The

completion of a user-defined task or the occurrence of a

user-selected event is indicated by using the extensive set

of interrupts provided.

In the BC mode, the BCRT can process multiple messages,

assist in scheduling message lists, and provide host-

programmable functions such as auto retry. The BCRT is

incorporated in systems with a variety of interrupt latencies

by using the Interrupt History List feature (see Exception

Handling and Interrupt Logging, page 33). The Interrupt

History List sequentially stores the events that caused the

interrupt in memory without losing information if a host

processor does not respond immediately to an interrupt.

5.0 SYSTEM INTERFACE

5.1 DMA Transfers

The BCRT initiates DMA transfers whenever it executes

command blocks (BC mode) or services commands (RT

mode). DMAR initiates the transfer and is terminated by the

inactive edge of DMACK. The Address Enable (AEN)

input enables the BCRT to output an address onto the

Address bus.

The BCRT requests transfer cycles by asserting the DMAR

output, and initiates them when a DMAG input is received.

A DMACK output indicates

that the BCRT has control of the Data and Address buses.

The TSCTL output is asserted when the BCRT is actually

asserting the Address and Data buses.

To support using multiple bus masters in a system, the BCRT

outputs the DMAGO signal that results from the

DMAG signal passing through the chip when a BCRT bus

request was not generated (DMAR inactive). You can use

DMAGO in daisy-chained multimaster systems.

5.2 Hardware Interface

The BCRT provides a simple subsystem interface and

facilitates DMA arbitration. The user can configure the

BCRT to operate in a variety of memory-processor

environments including the pseudo-dual-port RAM and

standard DMA configurations.

For complete circuit description, such as arbitration logic

and I/O, please refer to the appropriate application note.

5.3 CPU Interconnection

Pseudo-Dual-Port RAM Configuration

The BCRT’s Address and Data buses connect directly to

RAM, with buffers isolating the BCRT’s buses from those

of the host CPU (figures 3a and 3b). The CPU’s memory

control signals (RD, WR, and MEMCSI) pass through the

BCRT and connect to memory as RRL, RWR,

and MEMCSO.

Standard DMA Configuration

The BCRT’s and CPU’s data, address, and control signals

are connected to each other as shown in figures 3c and 3d.

The RWR, RRL, and MEMCSO are activated after DMAG

is asserted.

In either case, the BCRT’s Address and Data buses remain

in a high-impedance state unless the CS and RD signals are

active, indicating a host register access; or TSCTL is

asserted, indicating a memory access by the BCRT. CPU

attempts to access BCRT registers are ignored during BCRT

memory access. Inhibit DMA transfers by using the Busy

function in the Remote Terminal Address Register while

operating in the Remote Terminal mode.

The designer can use TSCTL to indicate when the BCRT is

accessing memory. AEN is also available (use is optional),

giving the CPU control over the BCRT’s Address bus. A

DMA Burst (BURST) signal indicates multiple

DMA accesses.

Register Access

Registers 0 through 13 are accessed with the decode of the

four LSBs of the Address bus (A0-A3) and asserting CS.

Pulse either RD or WR for multiple register accesses

BCRT-19

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