80930HD Просмотр технического описания (PDF) - Intel

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80930HD

UNIVERSAL SERIAL BUS HUB PERIPHERAL CONTROLLER

Intel 

8x930Hx UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLER

3.0 PINOUT

Figure 4 illustrates a diagram of the 8x930HD/HE PLCC package. Table 6 and Table 8 contain indexes of the

pin arrangement. Table 10 contains the signal descriptions for all pins.

.

AD7 / P0.7 10

AD6 / P0.6 11

AD5 / P0.5 12

AD4 / P0.4 13

AD3 / P0.3 14

AD2 / P0.2 15

AD1 / P0.1 16

AD0 / P0.0 17

VSSP 18

VCCP 19

P3.0 / RXD 20

P3.1 / TXD 21

P3.2 / INT0# 22

P3.3 / INT1# 23

P3.4 / T0 24

P3.5 / T1 25

P3.6 / WR# 26

View of component as

mounted on PC board

60 UPWEN#†/DP5†

59 OVRI#†/DM5††

58 DP1

57 DM1

56 Reserved

55 DP0

54 DM0

53 ECAP

52 VSSP

51 VCCP

50 SOF#

49 DP3

48 DM3

47 Reserved

46 DP2

45 DM2

44 PLLSEL0

NOTE:

Reserved pins must be left unconnected.

† Specific to the 8x930HD/HE

†† Specific to the 8x930HF/HG

Figure 4. 8x930HD/HE and 8x930HF/HG 68-pin PLCC Package

A4421-01

6

ADVANCE INFORMATION

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