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LTC1662IMS8

Ultralow Power, Dual 10-Bit DAC in MSOP

Linear Technology 

LTC1662

TYPICAL PERFOR A CE CHARACTERISTICS

Max/Min Output Voltage vs Source/

Sink Output Current (VCC = 3V)

3.0

2.7

CODE = 1023

2.4

2.1

1.8

1.5

VREF = VCC

TA = 25°C

1.2

0.9

0.6

CODE = 0

0.3

0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

OUTPUT SOURCE/SINK CURRENT (mA)

1662 G16

Large-Signal Step Response

5

4

3

2

1

VREF = VCC = 5V

10% TO 90% STEP

0

0

TIME (0.5ms/DIV)

1662 G17

Output Minimum Series

Resistance vs Load Capacitance

180

160

140

120

100

80

60

40

20

0

100p 1000p 0.01µ 0.1µ 1µ

CAPACITANCE (F)

10µ 100µ

1662 G18

PI FU CTIO S

CS/LD (Pin 1): Serial Interface Chip Select/Load Input.

When CS/LD is low, SCK is enabled for shifting data on SDI

into the register. When CS/LD is pulled high, SCK is

disabled and the operation(s) specified in the Control

code, A3-A0, is (are) performed. CMOS and TTL compat-

ible.

SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL

compatible.

SDI (Pin 3): Serial Interface Data Input. Input word data on

the SDI pin is shifted into the 16-bit register on the rising

edge of SCK. CMOS and TTL compatible.

REF (Pin 4): Reference Voltage Input. 0V ≤ VREF ≤ VCC.

VOUT A, VOUT B (Pins 8,5): DAC Analog Voltage Outputs.

The output range is

0 ≤ VOUTA,VOUTB ≤ VREF  11002234

VCC (Pin 6): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.

GND (Pin 7): System Ground.

DEFI ITIO S

Differential Nonlinearity (DNL): The difference between

the measured change and the ideal 1LSB change for any

two adjacent codes. The DNL error between any two codes

is calculated as follows:

DNL = (∆VOUT – LSB)/LSB

where ∆VOUT is the measured voltage difference between

two adjacent codes.

Full-Scale Error (FSE): The deviation of the actual full-

scale voltage from ideal. FSE includes the effects of offset

and gain errors (see Figure 2).

Gain Error (GE): The deviation from the slope of the ideal

DAC transfer function, expressed in LSBs at full scale.

Integral Nonlinearity (INL): The deviation from a straight

line passing through the endpoints of the DAC transfer

curve (Endpoint INL). Because the output cannot go below

zero, the linearity is measured between full scale and the

lowest code which guarantees the output will be greater

than zero. The INL error at a given input code is calculated

as follows:

INL = [VOUT – VOS – (VFS – VOS)(code/1023)]/LSB

6

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