RS5C313 Просмотр технического описания (PDF) - RICOH Co.,Ltd.
Номер в каталоге
Компоненты Описание
Список матч
RS5C313 Datasheet PDF : 32 Pages
| |||
RS5C313
2.1-2 (BSY)
When the BSY bit is 1, the clock and calendar counters are being updated. Consequently, write operation should be performed
for the counters when the BSY bit is 0. Meanwhile, read operation is normally performed for the counters when the BSY bit is 0,
but can be performed without checking the BSY bit as long as appropriate software is provided for preventing read errors(Refer
to the item 11.3 Read Operation from Clock and Calendar Counters). The BSY bit is set to 1 in the following three cases:
(1) Adjustment of second digits by
±30 seconds
MAX. 122.1µs
Setting of the ADJ bit to 1 Completion of second digit adjustment
(2) Second digit increment by 1
(Subject to 1-second digit carry
when the WTEN bit is switched
from 0 to 1)
MAX.91.6µs
Setting of the WTEN bit to 1 End of second digit increment by 1
(3) Ordinary 1-second digit carry
91.6µs
2.1-3 (WTEN)
End of second digit carry pulse
The WTEN bit should be set to 0 to check that the BSY bit is 0 when performing read and write operations for the clock and
calendar counters. For read operation, the WTEN bit may be left as 1 without checking the BSY bit as long as appropriate
measures such as read repetition are provided for preventing read errors(Refer to the item 11.3 Read Operation from Clock
and Calendar Counters). The WTEN bit should be set to 1 after completing read and write operations, or will automatically
be set to 1 by switching the CE pin to the low level. If 1-second digit carry occurs when the WTEN bit is 0, a second digit
increment by 1 occurs when the WTEN bit is set to 1.
Note
If the WTEN bit is 0 for 1/1024 second and more, second digit increment by 1 may not occur. (Refer to the item 11.3
Read Operation from Clock and Calendar Counters).
2.1-4 (XSTP)
The XSTP bit senses the ocilllator halt. When the CE pin is held at the low level, the XSTP bit is set to 1 once the crystal
oscillator is stopped after initial power-on or supply voltage drop and left to be 1 after it is restarted. When the CE pin is held
at the high level, the XSTP bit is left as it was when the CE pin was held at the low level without checking oscillation stop. As
such, the XSTP bit can be used to validate clock and calendar count data after power-on or supply voltage drop. The XSTP bit
is set to 0 when write operation is performed for the control register (at Eh) (during normal oscillation).
2.1-5 (12/24)
The 12/24 bit specifies time digit display in BCD code.
24-hour time display system 12-hour time display system 24-hour time display system 12-hour time display system
00
12(AM12)
12
32(PM12)
01
01(AM 1)
13
21(PM 1)
02
02(AM 2)
14
22(PM 2)
03
03(AM 3)
15
23(PM 3)
04
04(AM 4)
16
24(PM 4)
05
05(AM 5)
17
25(PM 5)
06
06(AM 6)
18
26(PM 6)
07
07(AM 7)
19
27(PM 7)
08
08(AM 8)
20
28(PM 8)
09
09(AM 9)
21
29(PM 9)
10
10(AM10)
22
30(PM10)
11
11(AM11)
23
31(PM11)
Either the 12-hour or 24-hour time display system should be selected before time setting (e.g. during initialization after power-on).
9
Share Link: 