MC100EL59
AC CHARACTERISTICS VCC= 5.0 V; VEE= 0.0 V or VCC= 0.0 V; VEE= –5.0 V (Note 1.)
–40°C
25°C
Symbol
Characteristic
Min Typ Max Min Typ Max
fmax
Maximum Toggle Frequency
TBD
TBD
tPLH
Propagation
DATA to Q/Q 340
690 340
690
tPHL
Delay
SEL to Q/Q 340
690 340
690
COM_SEL to Q/Q 340
690 340
690
tskew
Output–Output Skew
Any Dn, Dm to Q
100
100
tJITTER
Cycle–to–Cycle Jitter
TBD
TBD
tr
Output Rise/Fall Times Q
tf
(20% – 80%)
1. VEE can vary +0.8 V / –0.5 V.
200
540 200
540
85°C
Min Typ Max Unit
TBD
GHz
340
690 ps
340
690
340
690
ps
100
TBD
ps
200
540 ps
Driver
Device
Q
Qb
50 W
D
Receiver
Device
Db
50 W
V TT
V TT = V CC – 2.0 V
Figure 1. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 – Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
– ECLinPS Circuit Performance at Non–Standard VIH Levels
AN1405
– ECL Clock Distribution Techniques
AN1406
– Designing with PECL (ECL at +5.0 V)
AN1503
– ECLinPS I/O SPICE Modeling Kit
AN1504
– Metastability and the ECLinPS Family
AN1560
– Low Voltage ECLinPS SPICE Modeling Kit
AN1568
– Interfacing Between LVDS and ECL
AN1596
– ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650
– Using Wire–OR Ties in ECLinPS Designs
AN1672
– The ECL Translator Guide
AND8001 – Odd Number Counters Design
AND8002 – Marking and Date Codes
AND8020 – Termination of ECL Logic Devices
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