SAA7214 Просмотр технического описания (PDF) - Philips Electronics

Номер в каталоге

Компоненты Описание

Список матч

SAA7214

Transport MPEG2 source decoder

Philips Electronics 

Philips Semiconductors

Transport MPEG2 source decoder

Preliminary specification

SAA7214

FEATURES

General features

• Conditional access descrambling DVB-compliant

• Stream demultiplexing (TS, PES, program and

proprietary streams)

• Internal PR3001 32-bit RISC processor running at

40.5 MHz

• Low-power sleep modes supported across the chip

• Comprehensive driver software and development tool

support

• Package: SQFP208.

The following sections specify the features in more detail,

in the form of a feature matrix.

External interfaces

The SAA7214 supports the following external interfaces:

• Versatile compressed stream input at 108 Mbits/s

• A 16-bit microcontroller extension bus supporting

DRAM, Flash, (E)PROM and external memory mapped

• I/O devices. It also supports a synchronous interface to

communicate with the integrated MPEG AVGD decoder

SAA7215 at 40.5 Mbytes.

• an IEEE 1284 interface (Centronics) supporting master

and slave modes. Usable as a general purpose port

• A dedicated interface to IEEE 1394 devices (such as

Philips’ PDI 1394 chip set)

• Two UART (RS232) data ports with DMA capabilities

(≤187.5 kbits/s) including hardware flow control RxD,

TxD, RTS and CTS for modem support

• An elementary UART with DMA capabilities,(e.g.

dedicated to front panel devices for instance)

• Two dedicated smart-card reader interfaces (ISO 7816

compatible) with DMA capabilities

• Two I2C-bus master/slave transceivers supporting the

standard (100 kbit/s) and fast (400 kbits/s) I2C-bus

modes

• 32 general purpose, bidirectional I/O interface pins, the

first 8 bits may also be used as interrupt inputs

• One PWM output (8-bit resolution)

• A GP/HS interface supporting stream recording through

IEEE 1394 IC

• A JTAG interface for board test support.

CPU related features

The SAA7214 contains an embedded RISC CPU, which

incorporates the following features:

• A 32-bit PR3001 core

• 1 kbyte data, and 4 kbytes Instruction caches

(write-through style)

• A programmable low-power mode, including wake-up

on interrupt

• A memory management unit

• Two fully independent 24-bit timers and one 24-bit timer

including watchdog facilities

• A real-time clock unit (active in sleep mode)

• Built-in software debug support

• An on-chip 4 kbytes SRAM for storing code which needs

fast execution.

MPEG2 systems features

MPEG2 systems features of the SAA7214 include the

following

• Parsing of TS, PS (HW) and proprietary (SW) data

streams. Maximum input rate is 108 Mbits/s

• A real-time, DVB compliant descrambler core,

incorporating storage for up to 6 control word pairs

• HW section filtering based on 32 different PIDs with a

flexible number of filter conditions (8 or 4 byte condition

+ 8 or 4 byte mask) per PID and a total filter capacity of

40 (8 byte condition checks) or up to 80 (4 byte condition

checks) filter conditions.

• 4 TS/PES filters for retrieval for data at TS or PES level

for applications such as subtitling, TXT or retrieval of

private

• Data

• Flexible DMA based storage of the 32 section sub

streams and 4 TS/PES data substreams in the external

memory

2001 Mar 28

2

Share Link: