Timing Diagrams
HI5960
CLK
50%
D13-D0
IOUT
ERROR BAND
tSETT
tPD
FIGURE 2. OUTPUT SETTLING TIME DIAGRAM
tPW1
tPW2
CLK
D13-D0
tSU
tSU
tHLD
V
GLITCH AREA = 1/2 (H x W)
HEIGHT (H)
WIDTH (W)
t (ps)
FIGURE 3. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
tSU
tHLD
tHLD
50%
tPD
tSETT
IOUT
tPD
tSETT
tPD
tSETT
FIGURE 4. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
10