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TDA9103-USER

TDA9103 USER’S MANUAL DEMONSTRATION BOARD

STMicroelectronics 

TDA9103 USER’S MANUAL DEMONSTRATION BOARD

III - GUIDELINES FOR LAYOUT AND WIRING

SGS-THOMSON realized a demonstration board

for TDA9103 scanning processor. Since this dem-

onstration board is expected to work properly while

connected to an existing monitor set with flying

wires, special attention must be paid to the possible

misfunctions that may be caused by the wiring.

As the precautions we took may be very useful also

in normal layouting, we listed them herebelow, to-

gether with other pieces of advice.

III.1 - General Statement on Ground Connec-

tion

The ground connectionto TDA9103 not only carries

the supply current, but is also the voltage reference

for various functions. Consequently, it should not

carry high currents with fast transients, like :

- Vertical scanning supply

- Supply for B+ converter

Which would introduce parasitic series voltages

(resistive and inductive).

This was made easier by completely separating the

power sources for vertical and B+. Inside a chassis,

this would necessitate separated ground pins in the

SMPS transformer for ±12V (Vertical) and 45..60V

(B+).

III.2 - Vertical Section

III.2.1 - Booster Part

The +12V and -12V supplies feed the booster in

first ; this way, since the ground point was kept

separated, the high currents implied in vertical

scanning will keep localised between the supplies

and the booster.

Other traditionalprecautions for the booster include

:

- Film capacitors C31 and C32 with low HF imped-

ance, near to the booster with short tracks (an

alternate solution is to connect C32 between pins

2 and 4) ;

- ”Boucherot cell” R41, C19, near to the booster

with short tracks ;

- The ground track to driver stage (TDA9103) is

connected to the foot of R40.

III.2.2 - TDA9103 Oscillator and Driver Stage

The vertical section has a dedicated reference volt-

age (pin 26) which should be filtered versus vertical

ground (pin 24). Pin 24 may be tied to pin 19

(General ground). All elements relative to Vertical

should be refered to Vertical ground (C4, C5, C40,

C41, C42, C43).

The oscillator capacitor C4 claims for special atten-

tion. The vertical sawtooth is obtained by charging

it at low rate, then discharging abruptly. The switch-

ing from ”discharge” to ”charge” is triggered when

reaching a low threshold. The loop constituted by

C4 and its connecting tracks may give rise to para-

sitic series voltage spikes if there is a switching

circuit at short distance (like the DC/DC converter

for B+) ; one such spike could randomly trigger

early switching to ”charge”, and the effect would be

a vertical vibration of the display. Such vibrations

usually occur for determined settings of the hori-

zontal phase.To avoid this, the loop including C4

must have minimal area, and all switching circuits

(SMPS, DC/DC converter, horizontal scanning)

should be kept remote.

III.3 - Horizontal Section

III.3.1 - Oscillator Stage

Like Vertical section, Horizontal section has dedi-

cated voltage reference (pin 5) and Ground (pin 4).

In order to maintain the horizontaljitter to the lowest

possible value, pin 4 should be kept NOT CON-

NECTED TO ANY OTHER GROUND (an internal

connectionalready exists with pins 19 and 24), and

pin 5 should be filtered versus pin 4. This mainly

concerns pins 1, 2, 3, 5, 10, 11, 12, 14, 15, 17.

Moreover, the components not relatedto horizontal

should not be connected to pin 4.

As for Vertical section, the capacitors with their

connectingtracks should not constitute large loops,

prone to catch parasitic spikes.

When the various DC inputs are controlled by a

PWM type DAC, the DAC filtering capacitor must

not be refered to pin 4, where it would produce

parasitic voltages, but to the microprocessor

ground ; furthermore, since there is some ripple

between these two grounds, a second filter cell is

needed, with its capacitor connected to pin 4. The

second filter resistors are not present on the dem-

onstration board.

III.3.2 - Output Stage

Usually, the horizontal scanning stage is remote

from the TDA9103 and the control signal has to be

transmitted at a distance.

When the signal is taken from pin 21, pin 20 should

be connected to GND, but not necessarily to pin 19

or near to the IC.

In the typical application implemented on present

board, the gate capacitance of Q2 will be charged

and discharged at quite high current for every fast

transition of pin 21. The current path is as follows :

- For Charge : +12V (the filtering capacitor) > Q10

> R44 > gate of Q2 > source of Q2 > minus of

filtering capacitor

- For Discharge : gate of Q2 > Q1 > source of Q2

9/10

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