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CXD1217 Просмотр технического описания (PDF) - Sony Semiconductor

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CXD1217 Datasheet PDF : 12 Pages
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CXD1217Q
V reset (VRI input)
When the VRI is input as shown in figure below, OSYNC can be reset at the same phase with the SYNC signal.
Counter State
1 2 3 4 5 67
SYNC Signal
VRI
CXD1217 internal clock (2fH)
(See Timing Chart Diagram)
V reset pulse
8 9 10 11 12 13 14 15
Falling edge permitted span
a
Rising edge is to be behind from point a
After reset SYNC OUT
9
10 11 12
13 14
Reset State
Since the falling edge point in the diagram above (marked with ) is the boundary of reset, if the falling edge
of the VRI input traverses that point, it causes 1/2H deviation to the reset state.
Accordingly, if resetting is applied between two similar systems whose frequency are different, the V to which
resetting is applied generates jitter of 1/2H. (When the resetting is applied continuously.)
LALT reset (LALTRI input)
Phase relation between LALTRI pulse polarity and 2fH is the same as in the case of V resetting.
Resetting operation is basically required only in the external synchronizing mode (GEN LOCK mode). However,
even in the internal synchronizing mode, it sometimes requires H and V outputs whose phases are deviated
against a certain output. In that case, it suffices to use two CXD1217s and conduct the operation as follows:
Clock
CXD1217
OHD1 OVD1
VRI2
CXD1217
VRI2
OHD2 OVD2
Input
Shift Reg.
Clock
Output
Delay
It suffices to set IC-1 and IC-2 into INT mode.
By varying the Delay and Shift Reg. of the above diagram, any phases of OHD2 and OVD2 can be provided
against the respective OHD1 and OVD1.
3. Color framing
In the case of internal synchronization in the individual NTSC, PAL and PALM systems, the phase
relationships between SYNC of the 1st field and sub-carrier are kept stable regardless of the power supply
being ON or OFF. However, as the PAL and PALM systems are comprised of PLL, the absolute values
concerning the phase according to variation of the ambient temperature drifts.
–6–

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