L9805 Просмотр технического описания (PDF) - STMicroelectronics

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L9805

Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Full H-Bridge Driver

STMicroelectronics 

L9805

Address

Block

0031h

0032h

0033h

0034h-0035h

0036h-0037h

0038h-0039h TIM1

003Ah-003Bh

003Ch-003Dh

003Eh-003Fh

0040h

0041h

0042h

0043h

0044h-0045h

0046h-0047h

0048h-0049h TIM2

004Ah-004Bh

004Ch-004Dh

004Eh-004Fh

0050h to

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0060h to

006Fh

CAN

0070h

0071h

0072h

ADC

Register La-

bel

T1CR2 ..

T1CR1 ..

T1SR ..

T1IC1HR ..

T1IC1LR ..

T1OC1HR ..

T1OC1LR ..

T1CHR ..

T1CLR ..

T1ACHR ..

T1ACLR ..

T1IC2HR ..

T1IC2LR ..

T1OC2HR ..

T1OC2LR ..

T2CR2 ..

T2CR1 ..

T2SR ..

T2IC1HR ..

T2IC1LR ..

T2OC1HR ..

T2OC1LR ..

T2CHR ..

T2CLR ..

T2ACHR ..

T2ACLR ..

T2IC2HR ..

T2IC2LR ..

T2OC2HR ..

T2OC2LR ..

Register name

Timer 1 Control Register2

Timer 1 Control Register1

Timer 1 Status Register

Timer 1 Input Capture1 High Register

Timer 1 Input Capture1 Low Register

Timer 1 Output Compare1 High Register

Timer 1 Output Compare1 Low Register

Timer 1 Counter High Register

Timer 1 Counter Low Register

Timer 1 Alternate Counter High Register

Timer 1 Alternate Counter Low RegisteR

Timer 1 Input Capture2 High Register

Timer 1 Input Capture2 Low Register

Timer 1 Output Compare2 High Register

Timer 1 Output Compare2 Low Register

Reserved: Write Forbidden

Timer 2 Control Register2

Timer 2 Control Register1

Timer 2 Status Register

Timer 2 Input Capture1 High Register

Timer 2 Input Capture1 Low Register

Timer 2 Output Compare1 High Register

Timer 2 Output Compare1 Low Register

Timer 2 Counter High Register

Timer 2 Counter Low Register

Timer 2 Alternate Counter High Register

Timer 2 Alternate Counter Low Register

Timer 2 Input Capture2 High Register

Timer 2 Input Capture2 Low Register

Timer 2 Output Compare2 High Register

Timer 2 Output Compare2 Low Register

RESERVED

CANISR ..

CANICR ..

CANCSR ..

CANBRPR ..

CANBTR ..

CANPSR ..

CAN Interrupt Status Register

CAN Interrupt Control Register

CAN Control/Status Register

CAN Baud Rate Prescaler

CAN Bit Timing Register

CAN Page Selection

CAN First address to

last address of PAGE X

ADCDRH ..

ADCDRL ..

ADCCSR ..

ADC Data Register High

ADC Data Register Low

ADC Control/Status Register

Reset

Status

00h

00h

xxh

xxh

xxh

xxh

xxh

FFh

FCh

FFh

FCh

xxh

xxh

xxh

xxh

Remarks

R/W

R/W

Read Only

Read Only

Read Only

R/W

R/W

Read Only

Read Only

Read Only

Read Only

Read Only

Read Only

R/W

R/W

00h

R/W

00h

R/W

xxh

Read Only

xxh

Read Only

xxh

Read Only

xxh

R/W

xxh

R/W

FFh

Read Only

FCh Read Only

00h

Read Only

00h

Read Only

xxh

Read Only

xxh

Read Only

xxh

R/W

xxh

R/W

00h

R/W

00h

R/W

00h

R/W

00h

R/W

23h

R/W

00h

R/W

--

see page map-

ping and regis-

ter description

00h

Read Only

00h

Read Only

20h

R/W

10/103

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