W83194BR-KT Просмотр технического описания (PDF) - Winbond
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W83194BR-KT Datasheet PDF : 13 Pages
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* - Internal 120kΩ pull-up
W83194BR-KT
PRELIMINARY
4.1 Crystal I/O
SYMBOL
Xin
Xout
PIN
I/O
FUNCTION
4
IN Crystal input with internal loading capacitors and
feedback resistors.
5
OUT Crystal output at 14.318MHz nominally.
4.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs
SYMBOL
CPU_C0$
CPU_T0$
CPUT_CS
SDRAM [ 0 :12]
PCICLK_F^/
*MODE1
PCICLK1^/*FS1
PIN
43
44
46
17,18,20,21,28,
29,31,32,34,
35,37,38,40
7
8
PCICLK2^/SEL24_48*
10
PCICLK ^[ 3 : 4 ]
PCICLK 5
BUFFER IN
RESET$/*PD#
11,12,13
15
41
I/O
OD
OUT
OUT
I/O
I/O
I/O
OUT
IN
I/O
FUNCTION
CPU_C0 and CPU_T0 are the differential open drain
CPU clocks for AMD AthloneTM CPU. CPUT_CS is
the open drain pin for the chipset. It has the same
phase relationship as CPU_T0.
CPUT_CS is the output pin for the chipset. It has the
same phase relationship as CPU_T0.
SDRAM clock outputs. Fanout buffer outputs from
BUFFER IN pin.(Controlled by chipset) They are
disabled when PD# is set LOW.
Free running PCI clock during normal operation.
Latched Input. Mode1=1(default), Pin 41 is RESET#
open drain. (4ms low active pulse when Watch Dog
time out), *Mode1=0, PD# input
Low skew (< 250ps) PCI clock outputs.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
Low skew (< 250ps) PCI clock outputs.
Latched input for at initial power up for H/W
selecting the output frequency of 24_48MHz.
SEL24_48*=1(default), pin25 is 24MHz,
SEL24_48=0, pin25 is 48MHz.
Low skew (< 250ps) PCI clock outputs.
PCICLK_F and PCICLK [1:4] are double strength
pins
PCICLK 5 is not..
Inputs to fanout for SDRAM outputs.
The all clocks will be stopped when this pin set to
LOW. Mode1=1(default), Pin41 is RESET$ open
drain. (4ms low active pulse when Watch Dog time
Publication Release Date: June 2000
-3-
Revision 0.43
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