W42C32-05G Просмотр технического описания (PDF) - Cypress Semiconductor

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W42C32-05G

Spread Spectrum Frequency Timing Generator

Cypress Semiconductor 

W42C32-05

Application Information

Recommended Circuit Configuration

For optimum performance in system applications the power

supply decoupling scheme shown in Figure 4 should be used.

VDD decoupling is important to both reduce phase jitter and

EMI radiation. The 0.1-µF decoupling capacitor should be

placed as close to the VDD pin as possible, otherwise the in-

creased trace inductance will negate its decoupling capability.

The 10-µF decoupling capacitor shown should be a tantalum

type. For further EMI protection, the VDD connection can be

made via a ferrite bead, as shown.

The 16-pF XTAL load capacitors can be used to raise the inte-

grated 12-pF capacitors up to a total load of 20 pF on the

crystal.

Recommended Board Layout

Figure 4 shows a recommended 2-layer board layout.

C1 =16 pF

C2 = 16 pF

XTAL1

Ground

CLKOUT

33Ω

(Modulated Output)

1

2

3

4G

5G

6

7

8

33Ω

REFOUT

16

15

14

13

12

C5

11

G (Via to ground plane)

C6

10

G

Voltage Supply Input

9

(3.3V, 5.0V)

Ferrite Bead

C3 = 0.1 µF

C4 = 10 µF

C1, C2 = XTAL load capacitors.

Typical value is 16 pF.

C3, C5, C6 = High frequency supply decoupling

capacitor (0.1-µF recommended).

C4 = Common supply low frequency

decoupling capacitor (10-µF tantalum

recommended).

33Ω = Match value to line impedance.

Ground

Figure 4. Recommended Board Layout (2-Layer Board)

Ordering Information

Ordering Code

Freq. Mask

Code

W42C32

05

Document #: 38-00808

Package

Name

G

Package Type

16-pin Plastic SOIC (300-mil)

7

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