U631H256 Просмотр технического описания (PDF) - Zentrum Mikroelektronik Dresden AG
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U631H256 Datasheet PDF : 12 Pages
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U631H256
SoftStore 32K x 8 nvSRAM
Features
F High-performance CMOS non-
volatile static RAM 32768 x 8 bits
F 25, 35 and 45 ns Access Times
F 10, 15 and 20 ns Output Enable
Access Times
F Software STORE Initiation
F Automatic STORE Timing
F 105 STORE cycles to EEPROM
F 10 years data retention in
EEPROM
F Automatic RECALL on Power Up
F Software RECALL Initiation
F Unlimited RECALL cycles from
F EEPROM
Unlimited Read and Write to
SRAM
F Single 5 V ± 10 % Operation
F Operating temperature range
0 to 70 °C
-40 to 85 °C
F CECC 90000 Quality Standard
F ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code Num-
F bers)
Packages:PDIP28 (300 mil)
PDIP28 (600 mil)
SOP28 (330 mil)
Description
The U631H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U631H256 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through software sequences.
The U631H256 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or write
accesses intervene in the sequence
or the sequence will be aborted.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile
information is transferred into the
SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U631H256 is pin compatible
with standard SRAMs.
Pin Configuration
Pin Description
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7 PDIP 22
8 SOP 21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
December 12, 1997
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
1
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