XRT71D00(2000) Просмотр технического описания (PDF) - Exar Corporation
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XRT71D00 Datasheet PDF : 18 Pages
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E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER XRT71D00
PIN DESCRIPTION
REV. 1.01
PIN #
20
21
22
23
24
25
26
27
28
29
NAME
ICT
GND
RRClk
RRNEG
NC
NC
RRPOS
VDD
Ch_Addr_0
E3/DS3
(CS)
TYPE
I
***
O
O
***
***
O
***
I
I
DESCRIPTION
In Circuit Testing Input. Active low.
With this pin tied to ground, all output pins will be in high impedance mode
for in-circuit-testing.
For normal operation this input pin should be tied to VDD.
Digital Ground:
Receive Output (De-jittered) Clock.
Output the de-jittered or smoothed clock if the jitter attenuator is enabled.
The de-jittered data, RRPOS/RRNEG are clocked to this signal.
If ClkES is “low”, RRPOS/RRNEG will be updated at the falling edge of
RRClk.
If ClkES is “high”, RRPOS/RRNEG will be updated at the rising edge of
RRClk.
Receive Negative Data (De-Jittered) Output.
De-jittered negative data output. Updated on the rising or falling edge of
RRClk, depending upon the state of the ClkES input pin (or bit-field set-
ting).
This pin is not connected internally.
This pin is not connected internally.
Receive Positive Data (De-Jittered) Output.
De-jittered positive data output. Updated on the rising or falling edge of
RRClk (see pin 9), depending upon the state of the ClkES input pin (or bit-
field setting).
Digital Positive Supply Voltage: 3.3V or 5.0V ± 5%
Channel Addr_0 Assignment Input.
This input pin, along with pin 15 permits the user to assign a “Channel
Address” to the XRT71D00.
E3/DS3 Select Input/Chip Select Input:
The function of this pin depends on whether the XRT71D00 is configured
in Host or Hardware mode.
Hardware Mode—E3/DS3* Select Input:
This pin along with the STS-1 mode select pin (pin 8) selects the operating
mode. The following table provides the configuration:
STS-1
0
0
1
1
E3/DS3*
0
1
0
1
XRT71D00 Operating Mode
DS3 (44.736 MHz)
E3 (34.368 MHz)
STS-1 (51.84 MHz)
E3 (34.368 MHz)
HOST Mode—Chip Select Input:
An active-low input enables the serial interface. (Note: This pin is internally
pulled “high”.)
30
VDD
*** Digital Positive Supply Voltage: 3.3V or 5.0V ± 5%
31
RPOS
I Receive Positive Data (Jittery) Input.
Data that is input on this pin is sampled on either the rising or falling edge
of RClk depending on the setting of the ClkES pin (pin 10).
If ClkES is “high”, then RPOS will be sampled on the falling edge of RClk.
If ClkES is “low”, then RPOS will be sampled on the rising edge of RClk.
32
NC
*** This pin is not connected internally.
6
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