M37640E8 Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC
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M37640E8 Datasheet PDF : 172 Pages
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7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
2.1.3 Index Registers X and Y
Both index registers X and Y are 8-bit registers. In the absolute addressing modes, the contents of
these registers are added to the value of the OPERAND to specify the real address.
In the indirect X addressing mode, the value of the OPERAND is added to the contents of register X
to specify the zero page basic address. The data at the basic address specifies the real address.
In the indirect Y addressing mode, the value of the operand specifies a zero page address. The data at
this address is added to the contents of register Y to produce the real address. These addressing modes
are useful for referencing subroutine tables and memory tables.
When the T flag in the processor status register is set high, the value contained in index register X points
to a zero page memory location that replaces the accumulator for most accumulator based instructions.
2.1.4 Stack Pointer
The stack pointer is an 8-bit register used during subroutine calls and interrupts. The stack is used to
store the current address data and processor status when branching to subroutines or interrupt routines.
The lower eight bits of the stack address are determined by the contents of the stack pointer. The
upper eight bits of the stack address are determined by the Stack Page Select Bit, bit 2 of the CPU
Mode Register A. If the Stack Page Select bit is “0”, then the RAM in the zero page (addresses
007016 to 00FF16) is used as the stack area. If the stack page select bit is “1” (the default value), then
the RAM in one page (addresses 010016 to 01FF16) is used as the stack area. The base of the stack
must be set in software, and stack grows towards lower addresses from that point. The operations of
pushing register contents onto the stack and popping them from the stack are shown in Figure 2-2.
2.1.5 Program Counter
The program counter (PC) is a 16-bit register consisting of two 8-bit sub-registers PCH and PCL. It is
used to indicate the address of the next instruction to be executed.
2-4
7/9/98
Central Processing Unit
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