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LTC1345ISW

Single Supply V.35 Transceiver

Linear Technology 

PI FU CTIO S

Y3 (Pin 22): Transmitter 3 Noninverting Output.

Z2 (Pin 23): Transmitter 2 Inverting Output.

Y2 (Pin 24): Transmitter 2 Noninverting Output

Z1 (Pin 25): Transmitter 1 Inverting Output.

LTC1345

Y1 (Pin 26): Transmitter 1 Noninverting Output.

VEE (Pin 27): Charge Pump Output. Connected to negative

terminal of capacitor C3.

C2 – (Pin 28): Capacitor C2 Negative Terminal.

FU CTIO TABLES

Transmitter and Receiver Configuration

S1

S2

TX# RX# REMARKS

0

0

—

—

Shutdown

1

0

1, 2, 3 1, 2

DCE Mode, RX3 Shut Down

0

1

1, 2 1, 2, 3 DTE Mode, TX3 Shut Down

1

1

1, 2, 3 1, 2, 3 All Active

Transmitter

INPUTS

OUTPUTS

CONFIGURATION S1 S2 T Y1 AND Y2 Z1 AND Z2 Y3 Z3

DTE

01 0

0

1

ZZ

DTE

01 1

1

0

ZZ

DCE or All ON

1X 0

0

1

01

DCE or All ON

1X 1

1

0

10

Shutdown

00 X

Z

Z

ZZ

Receiver

INPUTS

CONFIGURATION S1 S2 OE B – A

DTE or All ON

X 1 0 ≥ 0.2V

DTE or All ON

X 1 0 ≤ – 0.2V

DCE

1 0 0 ≥ 0.2V

DCE

1 0 0 ≤ – 0.2V

Disabled

XX 1

X

Shutdown

00 X

X

OUTPUTS

R1 AND R2 R3

1

1

0

0

1

Z

0

Z

Z

Z

Z

Z

TEST CIRCUITS

Y

50Ω

T

Y

VOD

125Ω

VOS 125Ω

50Ω

B

R

Z

50Ω

A

50Ω

OE

VOC = (VY + VZ)/2

Z

15pF

LTC1345 • F01

Figure 1. V.35 Transmitter/Receiver Test Circuit

RECEIVER

OUTPUT

1k

CL

VCC

S1

S2

LTC1345 • F02

Figure 2. Receiver Output Enable/Disable Timing Test Load

5

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