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L6256

12V COMBO

STMicroelectronics 

L6256

ELECTRICAL CHARACTERISTICS

Power On Reset Section

POR SPECIFICATIONS

Specification Parameter

Vcc max undervoltage detect trip point, Vuv

Vcc trip point hysteresis

Vdd undervoltage detect trip point Vuvd

Vdd trip point hysteresis

Max POR\ delay timing

Forcing current to reset POR_RC (for in circuit test only)

AC UV detection - nondetectable pulse Tuvmin (1)

AC UV detection - detectable pulse Tuvmax (1)

Required Value

4.06 to 4.3

1%

9.3 to 9.8 volts

1%

100 msecs

nominal 1 milliamp

1 µsec

20 µsecs

(1) AC detection test: done on either supply. With either supply at 0.2 volts above the trip point, a 1.2 volt negative pulse is applied.

Chip must not respond to pulse width of Tuvmin, and must respond to Tuvmax.

Symbol

Vmin

Vtcap

Vcth

Tstrech

Ttol %

Tpmin acc

Vlw

Iweak

Trise

Ipullup

Parameter

Required VCC or Vdd for valid

POR\@25°C (7)

Timing Cap timeout threshold

Timing Cap threshold

POR\ pulse strech width

POR\ pulse tolerance

external POR\ input required

pulse width

Voltage measurement point for

Tpmin

Pullup Current, POR\, steady

state (at 3V)

Rise time on POR\, internal

driver with 100pF load (2)

Pullup Current, POR\,

momentary

Test Condition

Min. Typ. Max. Unit

1.3

2.0

V

2/3 VCC

V

(10)

5

40

100 ms (5)

±20% (6)

300 ns (9)

0.8

V

100

µA

100

ns

3.2

mA

Notes:

(1) dVmarg% The margining limit is determined as a fraction of the actual chip margin circuitry.

(2) hysteresis on POR\ is optional.

Load: POR\ will see approximately 90 pF plus an external pullup source of approximately 6k ohms. No external bulk capacitance is used

on POR\.

(3) fall time measured from 2 volts to 0.8 volts.

(4) pulse width measured from Vporint volts on falling edge to 1.6 volts on rising edge.

(5) is capable of meeting this timing with a 0.1µF or less, 20% tolerance ceramic capacitor. Nominal design point, .047µF is 40 ms ±20%.

(6) Timing tolerance on POR pulse width irrespective of external parts.

(7) POR\ is valid if either Vcc or Vdd exceeds this voltage.

(8,9) Tpmin acc is the minimum POR\ pulse width which the combo must recognize as a valid external POR. This corresponds to the width of

the reset pulse from the processor. Pulse widths narrower than this may or may not be recognized. Tpmin rej is the value of pulse width

above which the combo should not recognize a pulse.

(10) Vbounce is caused by the transition between the external POR circuit and the internal POR clamp circuitry.

in order to prevent deadly embrace with the microprocessor. The specified value is needed with 3.3V logic circuitry.

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