LC72E32 Просмотр технического описания (PDF) - SANYO -> Panasonic
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LC72E32 Datasheet PDF : 15 Pages
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Option
No.
Description
1 WDT (watchdog timer) inclusion selection
2 Port A pull-down resistor inclusion selection
3 Cycle time selection
4 LCD port/general-purpose port selection
LC72E32
Selections
WDT included
No WDT
Pull-down resistors included
No pull-down resistors
2.67 µs
13.33 µs
40.00 µs
LCD ports
General-purpose output ports
Usage Notes
The LC72E32 is provided for development of LC7232N application programs and for LC7232N function evaluation.
The points listed below required attention when using the LC72E32.
1. Differences between the LC72E32 and the LC7232N
Item
LC72E32
LC7232N
Operating temperature (Topr)
10 to 40 °C
–40 to +85°C
Operation immediately
following power on
After the 75 ms power on reset period, the LSI internal
option settings are set up during a period of about 1 ms.
After that operation completes, program execution starts
with the program counter set to location 0.
After the 75 ms power on reset period, program execution
starts with the program counter set to location 0.
Input type of the A port
immediately following power on* No pull-down resistors
Pull-down resistors are included or not according to the
option specifications.
Output type of the S1 to S28
outputs immediately following
power on*
LCD ports
These pins function as either LCD ports or general-
purpose output ports according to the option
specifications.
Power-down detection voltage
(VDET)
Minimum: 3.0 V
Typical: 3.5 V
Maximum: 4.0 V
Minimum: 2.7 V
Typical: 3.0 V
Maximum: 3.3 V
IDD2
Conditions: VDD = 5.0 V, PLL stopped
CT = 2.67 µs (HOLD mode, Figure 1)
Typical: 2.7 mA
Conditions: VDD2, PLL stopped
CT = 2.67 µs (HOLD mode, Figure 1)
Typical: 1.5 mA
Current drain
IDD3
Conditions: VDD = 5.0 V, PLL stopped
CT = 13.33 µs (HOLD mode, Figure 1)
Typical: 1.7 mA
Conditions: VDD2, PLL stopped
CT = 13.33 µs (HOLD mode, Figure 1)
Typical: 1.0 mA
IDD4
Conditions: VDD = 5.0 V, PLL stopped
CT = 40.00 µs (HOLD mode, Figure 1)
Typical: 1.5 mA
Conditions: VDD2, PLL stopped
CT = 40.00 µs (HOLD mode, Figure 1)
Typical: 0.7 mA
The TEST1 and TEST2 pins
These are LSI test pins and must be connected to VSS.
These are LSI test pins and must be either left open or
connected to VSS.
Note: * This refers to the option setup time of about 1 ms that occurs following the period of about 75 ms from power application.
2. PLA and options
The LC72E32 uses location 2000H to 201FH as program memory for PLA pattern specification, and locations
2020H to 2033H for option specification. This option specification allows the LC72E32 to support option setups
identical to those available with the LC7232N.
No. 4741-8/15
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