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MP8831AN

Single 10-Bit ADC with Digitally Controlled References

Exar Corporation 

MP8831

digital inputs and AD[7:0] are programmed as digital

outputs. Please note that when DA[7:0] are used as

inputs they accept TTL level signals, when AD[7:0] are

used as inputs they accept CMOS level inputs.

While in either of the pass-through modes, CLK-A &

CLK-B should both be held high.

Test Mode (CNTL-A=low, CNTL-B=low)

This mode is used to test the gain and offset DACs. The

ADC reference voltages are output on the two MSB pins

of the AD bus, VRT on pin AD9 and VRB on pin AD8. The

data from the DA bus is read in to the DACs the same as

during normal conversion operation (i.e. on the rising

edges of CLK-A & CLK-B).

Controlling ADC Gain and Offset

The input range of the ADC is set by the voltages at its top

(VRT) and bottom (VRB) reference nodes. The Offset DAC

sets the voltage at the VRB node. The Gain DAC sets the

span VRT-VRB. The following equations relate the DAC

codes to the voltages at VRB & VRT:

VREF = voltage at VREF, pin 18

DOFFSET = Offset DAC code, 6 bits, OS[5:0]

DGAIN = Gain DAC code, 10 bits, GD[9:0]

ǒ Ǔ VRB +

0.178

)

DOFFSET

64

@ 0.170

@ VREF

ǒ Ǔ VRT – VRB +

DGAIN

1024

@ 2.82 @ VREF

NJǒ Ǔ Nj VRT +

DGAIN

1024

@ 2.82 @ VREF

) VRB

Note:

The output of the Gain DAC becomes non-linear when VRT,

calculated using the above equations, is higher than

VDD-1.6V. The ADC itself remains linear, but its input range,

set by the DACs, deviates from the calculated values. This

can only happen if VREF is larger than 1.068V.

Sensor

(CCD)

Difference

REF

10

VIN

AD[9:0]

MP8831

Reference

Input

DA[7:0]

8

CLK A

CLK B

Cntl A

Cntl B

Clocks

Controls

Micro Processor

or

Digital ASIC

Computer

Interface

RAM for

Gain & Offset

Data

R/W

Address

Rev. 1.00

Figure 6. General Scanner System Using the MP8831

10

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