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RS8234

ServiceSAR Controller

Conexant Systems 

network access products

ServiceSAR Controller

RS8234

Integrated Management

The RS8234 complies with ATM Forum specifications

UNI 3.1, T.M. 4.1 and all other relevent standards.

The RS8234 provides integrated traffic management

for all service categories, including constant bit rate

(CBR), variable bit rate (VBR) (single- and dual-leaky

bucket), real-time VBR, unspecified bit rate (UBR),

available bit rate (ABR), guaranteed frame rate (GFR)

(guaranteed MCR on UBR VCCs), and generic

flow control (GFC). The xBR traffic management block

automatically schedules each VCC according to user

assigned-parameters to maximize line utilization.

Advanced Architecture

The RS8234’s architecture is designed to minimize

and control host traffic congestion. The host manages

the RS8234 terminal using write-only control and

status queues. The control queues are also isolated

from their associated data buffers via buffer

descriptors, allowing the data buffers to hold payload

data only. For example, the host submits data for

transmit by writing buffer descriptor pointers to one

of 32 transmit queues. These entries may be thought

of as task lists for the ServiceSAR to perform. The 32

receive queues couple with the transmit structure to

create complete host peers. The RS8234 enables

control of traffic congestion through mechanisms like

receive buffer memory limitations (called firewalls),

and through explicit notification of congestion by the

host. This architecture reduces the control burden on

the host system while minimizing PCI bus utilization,

by eliminating reads across the PCI bus from host

control activities. It also provides control points to

manage congestion, which is critical for ABR.

The RS8234 System

The RS8234 consists of five separate coprocessors

(incoming and outgoing DMA, segmentation,

reassembly and xBR traffic manager), each of

which maintains state information in shared, off-chip

memory. This memory is controlled by the SAR

through the local bus interface, which arbitrates

access to the bus between the various coprocessors.

These coprocessors, though they run off the same

system clock, operate asynchronously from each

other. Communication between the coprocessors

takes place through on-chip FIFOs or through

queues in local memory.

The RS8234’s on-chip coprocessor blocks are

surrounded by high-performance PCI and UTOPIA

ports for glueless interface to a variety of system

components with full line-rate throughput and

low bus occupancy. Figure 1 illustrates these

functional blocks.

xBR Cell Scheduler

The cell scheduler rate-shapes all segmentation

traffic according to per-channel parameters. The

RS8234 supports eight user-assigned scheduling

priorities in addition to CBR. The user assigns a

priority to each channel. The user can further control

consumption of bandwidth by assigning peak cell

rate limits to four of those scheduling priorities.

The user sets the range of available transmission

rates for the scheduler by setting the size of the

dynamic schedule table and the duration of each

scheduling slot in the table.

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