YTD423 Просмотр технического описания (PDF) - Yamaha Corporation
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YTD423 Datasheet PDF : 11 Pages
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Supports ETSI ETS 300 012 [April 1992] and ANSI T1.605 operating modes
Leased line capability (JT-I430-a)
B channel I/O clock selection function
{ Internal clock mode: Inputs/outputs the B-channel data with 64 k, 56 k or 32 kHz internal clock
{ External clock mode (PCM Highway mode): Inputs/outputs the B channel data with a 128 kHz to
2048 kHz external clock
B channel selection function
{ Internal clock mode: Selects/switches B channel I/O pins
{ External clock mode (PCM Highway mode): Selects/switches B channel time slots
Multiframing capability
Abundant Test functions (for testing and maintenance)
{ Three kinds of loop-back modes (Loop-back 1 to 3)
{ INFO signals output for testing
{ Test pulse output for pulse shape evaluation
INFO1 transmission and INFO4 reception monitor pins
SLEEP monitor pin
I.430 transmission frame phase adjustment function
2. Layer 2 function
Conforms to ITU-T Recommendation Q.920 and Q.921 [1992 edition] and TTC Standard JT-Q920 and
JT-Q921 [1993 edition] (default)
{ HDLC frame control (Flag control, FCS generation/checking, automatic zero insertion/deletion,
abort pattern transmission/detection, etc.)
{ LAP-D status control (sequence control, ow control, SAPI control)
{ Built-in timer for time-out check
Supports ETSI ETS 300 125 [September 1991], National ISDN-1/2, AT&T 5ESS 5E9 and Nortel DMS-
100 S208-6 operating modes
Multi-link capability (circuit switching, packet switching)
Automatic assigned TEI/non-automatic assigned TEI (VC/PVC)
Leased line mode (disable layer 2 function)
3. Layer 3 interface function
Connects to 8-bit or 16-bit microprocessor (8086 family, Z80 family, 6800 family and 68000 family)
Operates in one of two data transfer modes
{ DMA transfer mode (with the built-in 24-bit address DMA controller)
{ I/O transfer mode (with the built-in FIFO)
Primitive logical interface
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