CY7C1350-80AC Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1350-80AC

128Kx36 Pipelined SRAM with NoBL™ Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1350

Description Table for details) inputs is latched into the device

and the write is complete.

The data written during the Write operation is controlled by

BWS[3:0] signals. The CY7C1350 provides byte write capabil-

ity that is described in the Write Cycle Description table. As-

serting the Write Enable input (WE) with the selected Byte

Write Select (BWS[3:0]) input will selectively write to only the

desired bytes. Bytes not selected during a byte write operation

will remain unaltered. A Synchronous self-timed write mecha-

nism has been provided to simplify the write operations. Byte

write capability has been included in order to greatly simplify

Read/Modify/Write sequences, which can be reduced to sim-

ple byte write operations.

Because the CY7C1350 is a common I/O device, data should

not be driven into the device while the outputs are active. The

Output Enable (OE) can be deasserted HIGH before present-

ing data to the DQ[31:0] and DP[3:0] inputs. Doing so will

Cycle Description Truth Table[1,2,3,4,5,6]

three-state the output drivers. As a safety precaution, DQ[31:0]

and DP[3:0] are automatically three-stated during the data por-

tion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1350 has an on-chip burst counter that allows the

user the ability to supply a single address and conduct up to

four WRITE operations without reasserting the address inputs.

ADV/LD must be driven LOW in order to load the initial ad-

dress, as described in the Single Write Access section above.

When ADV/LD is driven HIGH on the subsequent clock rise,

the chip enables (CE1, CE2, and CE3) and WE inputs are ig-

nored and the burst counter is incremented. The correct

BWS[3:0] inputs must be driven in each cycle of the burst write

in order to write the correct bytes of data.

Operation

Deselected

Address

Used

External

ADV/

CE CEN LD/

WE BWSx CLK

Comments

1

0

L

X

X L-H

I/Os three-state following next rec-

ognized clock

Suspend

-

X

1

X

X

X L-H

Clock ignored, all operations sus-

pended

Begin Read

External

0

0

0

1

X L-H

Address latched

Begin Write

External

0

0

0

0

Valid L-H

Address latched, data presented

two valid clocks later

Burst Read

Operation

Internal

X

0

1

X

X L-H

Burst Read operation. Previous ac-

cess was a Read operation. Ad-

dresses incremented internally in

conjunction with the state of Mode.

Burst Write Op- Internal

eration

X

0

1

X

Valid L-H

Burst Write operation. Previous ac-

cess was a Write operation. Ad-

dresses incremented internally in

conjunction with the state of

MODE. Bytes written are deter-

mined by BWS[3:0]

Notes:

1. X=Don't Care, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx =

Valid signifies that the desired byte write selects are asserted, see Write Cycle description table for details.

2. Write is defined by WE and BWS[3:0]. See Write Cycle Description table for details.

3. The DQ and DP pins are controlled by the current cycle and the OE signal.

4. CEN=1 inserts wait states.

5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.

6. OE assumed LOW.

5

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