Philips Semiconductors
SAE/J1850/VPW transceiver
Product data
AU5780A
SYMBOL
Pin BUS_IN
PARAMETER
CONDITIONS
CBIN
TDRXON;
tDRXOFF
TDRX_∆
Bus Input capacitance
Bus line to RX propagation delay, normal and
4x modes
Bus line to RX propagation delay mismatch,
normal and 4x modes
Measured at VBUSIN_HIGH or
VBUSIN_LOW to RX;
6 < VBATT < 24 V; of
RLOAD = 10 kW to 5V
tDRXOFF –tDRXON
Pin BATT
tlow_power time-out to low power state
TX low
NOTES;
1. TX < 0.9V for more than 4 ms
2. For 6V < VBATT < 9V the bus output voltage is limited by the supply voltage.
For 16V < VBATT < 24V (jump start) the load is limited by the package power dissipation
ratings; the duration of this condition is recommended to be less than 90 seconds.
3. Tested with a bus load of RLOAD = 400 W and CLOAD = 22,000 pF.
MIN. TYP. MAX. UNIT
10
20 pF
0.4
1.7 µs
–1.3
+1.3 µs
1
4 ms
2001 Jun 19
9