![](/html/Alliance/11801/page7.png)
Timing waveform of write cycle
tCYC
tCH
tCL
CLK
ADSP
tSS
tSH
ADSC
Address
tAS
tAH
A1
A2
WE
AS7C3128PFS32/36A
®
tSS
tSH
ADSC LOADS NEW ADDRESS
A3
tWS
tWH
BW[a:d]
CE0, CE2
tCSS
tCSH
CE1
ADV SUSPENDS BURST
tADVS
tADVH
ADV
OE
Data In
D(A1)
D(A2) D(A2Ý01) D(A2Ý01) D(A2Ý10) D(A2Ý11) D(A3)
tDS
tDH
D(A3Ý01) D(A3Ý10)
Note: ⊕ = XOR when MODE = High/No Connect; ⊕ = ADD when MODE = Low. Refer to Burst Sequence Table.
6/8/00
ALLIANCE SEMICONDUCTOR
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