AS7C3128PFS36A-3.5TQC Просмотр технического описания (PDF) - Alliance Semiconductor
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AS7C3128PFS36A-3.5TQC Datasheet PDF : 9 Pages
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AS7C3128PFS32/36A
®
Signal descriptions
Signal
I/O Properties Description
CLK
I CLOCK
Clock. All inputs except OE are synchronous to this clock.
A0–A16 I SYNC
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
DQ[a,b,c,d] I/O SYNC
Data. Driven as output when the chip is enabled and OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
CE0
I SYNC
inactive, ADSP is blocked. Refer to the SYNCHRONOUS TRUTH TABLE for more
information.
CE1, CE2 I SYNC
Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock edges
when ADSC is active or when CE1 and ADSP are active.
ADSP
I SYNC
Address strobe processor. Asserted LOW to load a new bus address or to enter standby mode.
ADSC
I SYNC
Address strobe controller. Asserted LOW to load a new address or to enter standby mode.
ADV
I SYNC
Advance. Asserted LOW to continue burst read/write.
GWE
I
SYNC default Global write enable. Asserted LOW to write all 36 bits. When High, BWE and WE0–WE3
= HIGH control write enable. This signal is internally pulled High.
BWE
I
SYNC default Byte write enable. Asserted LOW with GWE = HIGH to enable effect of WE0–WE3 inputs.
= LOW
This signal is internally pulled Low.
BW[a,b,c,d] I SYNC
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write
cycle. If all BW[a:d] are inactive the cycle is a read cycle.
OE
I ASYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is
synchronously enabled.
LBO
I
STATIC default Count mode. When driven High, count sequence follows Intel XOR convention. When
= HIGH
driven Low, count sequence follows linear convention. This signal is internally pulled High.18
FT
I STATIC
Flow-through mode.When low, enables single register flow-through mode. Connect to VDD
if unused or for pipelined operation.
ZZ
I ASYNC
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
DC output current
Storage temperature (plastic)
Temperature under bias
VDD, VDDQ
–0.5
VIN
–0.5
VIN
–0.5
PD
–
IOUT
–
Tstg
–65
Tbias
–65
+4.6
V
+4.6
V
VDDQ + 0.5
V
1.2
W
30
mA
+150
oC
+135
oC
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions may affect reliability.
6/8/00
ALLIANCE SEMICONDUCTOR
3
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