AS7C3128PFS36A-3.5TQC Просмотр технического описания (PDF) - Alliance Semiconductor
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AS7C3128PFS36A-3.5TQC Datasheet PDF : 9 Pages
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AS7C3128PFS32/36A
®
Functional description
The AS7C37C3128PFS32/36A family is a high performance CMOS 4 Mbit synchronous Static Random Access Memory
(SRAM) organized as 131,072 words × 32 or 36 bits and incorporates a two stage register-register pipeline for highest
frequency on any given technology.
Timing for this device is compatible with existing Pentium synchronous cache specifications. This architecture is suited for
ASIC, DSP (TMS320C6X), and PowerPC based systems in computing, datacomm, instrumentation, and telecommunications
systems. When using pipeline burst SRAMs, any turnaround from read-to-write and write-to-read, required the insertion of
two dead cycles. When reading data, a two cycle latency until data valid exists due to the nature of the dual register
architecture. When writing, data, address and controls are all presented simultaneously. Therefore two dead cycles are required
to clear the read pipeline before a write can occur. In a write-to-read transition, two dead cycles are again produced due to the
pipeline read latency. These penalties are eliminated in the AS7C3128KNTD32/36 architecture device.
Fast cycle times of 6/6.7/7.5/10 ns with clock access times (tCD) of 3.5/3.5/3.8/4 ns enable 167, 150, 133 and 100 MHz
bus frequencies. Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the
controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent
internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip
address register when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a
read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock
edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next
access of the burst when WE is sampled High, ADV is sampled Low, and both address strobes are High. Burst operation is
selectable with the MODE input. With MODE unconnected or driven High, burst operations use a Pentium count sequence.
With MODE driven LOW the device uses a linear count sequence, suitable for PowerPC and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enableGWE
writes all 32 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be
written by asserting BWE and the appropriate individual byte BW signal(s).
BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are
disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low.
Address is incremented internally to the next burst of address if BWn and ADV are sampled Low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and
ADSP follow.
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).
• Master chip select CE0 blocks ADSP, but not ADSC.
The AS7C3128K36P family operates from a 3.3V supply. I/O’s use a separate power supply that can operate at 2.5V or 3.3V.
This device is available in a 100-pin 14×20 mm TQFP package.
Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
CIN
CI/O
Signals
Address and control pins
I/O pins
Write enable truth table (per byte)
GWE
BWE
BWn
L
X
X
X
L
L
H
H
X
H
L
H
Key: X = Don’t Care, L = Low, H = High.
† Valid read.
Test conditions
Vin = 0V
Vin = Vout = 0V
WRITEn
T
T
F
F†
Max
Unit
5
pF
7
pF
2
ALLIANCE SEMICONDUCTOR
6/8/00
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